coreboot-kgpe-d16/src/soc
Divya Sasidharan 1ff0f54f03 soc/braswell: Add CPUID for D0 stepping
Original-Reviewed-on: https://chromium-review.googlesource.com/309122
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>

Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://review.coreboot.org/12727
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14 23:09:47 +01:00
..
broadcom/cygnus Correct some common spelling mistakes 2016-01-07 22:57:02 +01:00
imgtec/pistachio imgtec/pistachio: disable default RPU gate register values 2015-12-31 17:36:06 +01:00
intel soc/braswell: Add CPUID for D0 stepping 2016-01-14 23:09:47 +01:00
marvell/bg4cd arm/arm64: Generalize bootblock C entry point 2015-11-11 05:08:07 +01:00
mediatek/mt8173 tree: drop last paragraph of GPL copyright header from new files 2016-01-13 20:35:40 +01:00
nvidia Correct some common spelling mistakes 2016-01-07 22:57:02 +01:00
qualcomm/ipq806x cbfs_spi: enable CBFS access in early romstage 2015-12-03 14:17:04 +01:00
rockchip/rk3288 google/veyron*: Pulse the i2c clock once if sda was low 2015-11-18 16:29:16 +01:00
samsung soc/samsung/exynos5250: Implement hard_reset() 2015-12-16 00:41:03 +01:00
ucb/riscv tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00