The read and write routines take a number of bytes to write, which
should be 1,2, or 4. We now return an error if an invalid size
is specified.
Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12936
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.
Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This just tells the OS that it can use the 16GB of address space
at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit
physical address space.
This could be hardcoded into the UMEM definition, but doing it this way
makes it more plain what it's doing, and allows for modification
to put it just above the top of upper memory, similar to what is done
with the standard PCI region above the top of low memory.
Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12791
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so
disable them by default for now.
Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions. Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime. This should allow one rom to be used for all revisions.
The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues. This
seems like the best way to eliminate the need for that symbol.
Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The RPU Clock register defaults to on for all clocks.
This is modified to OFF, and the MIPS clock control modified to ON,
by default. This is because the linux kernel will manage the
clocks at all times, but the RPU can only disable clocks if the WIFI
module has been loaded.
Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role
of SRAM) was placed at a 4K aligned address, resulting in a size of
408KB.
Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The base address for the I2C dividers (DIV1 and CLOCKOUT)
was erroneously set to the toplevel clock controller base
address and not to the correct peripherals clock controller
base address.
Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This region must be mapped uncached. This is necesary for an
U-boot payload which will obtain all register base addresses
as physical addresses from the device tree and will use them
as such.
Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When used with a U-boot payload it will need this region
identity mapped also, so we're defining it in preparation
for that functionality.
Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12768
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Use SYS PLL in integer mode by default to reduce jitter.
DSMPD_MASK is defined and can be used to switch to fractional mode.
Tested on pistachio bring up board.
Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
In order for a U-boot payload to work properly the soc_registers
region (device registers) needs to be mapped as uncached.
Therefore, add a coherency argument to the identity mapping funcion
which will establish the type of mapping.
Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12769
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This requires changes the interface that sets up the system
PLL to support a given reference devider value and given
feedback value.
Also, this requires a change in the dividers used for UART,
USB, I2C setup.
Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EHCI debug device setup code was removed from broadwell in
commit 49ee5ef: http://review.coreboot.org/11874
However the generic device setup code is in the southbridge/common/intel
directory while broadwell is in the soc directory so this is not used.
Add it back to the broadwell soc to fix undefined reference compile
errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'.
This was tested to compile and produce romstage and ramstage output on a
google/samus board.
Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The port0 and port1 registers were swapped, which meant it did
not work to apply the DTLE settings to the correct SATA port.
This was tested on an unreleased mainboard but is verified with
the documentation to be the correct register addresses now.
Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12793
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Locking down the SPI controller with a specific opcode menu kills
the SPI console. Skip this when the SPI console config option is
enabled.
This was tested using an em100 and google/samus board to ensure
the console output does not stop at the finalize step.
Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12792
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Upcoming versions of IASL give a warning about unused methods. This
adds an operation after the read to use the local variable and avoid
the warning.
The warning can be completely disabled on the command line, but as it
can find real issues, my preference is to not do that.
Fixes warnings:
dsdt.aml 640: Store (CTMP, Local0)
Warning 3144 - Method Local is set but never used ^ (Local0)
Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Baytrail has I2c Busses 0 to 6, so is supposed to error out
if the I2c driver is called with 7 or greater. Due to an off-by-one
error it could be called with bus 7.
Fixes coverity warning:
CID 1287074 (#1 of 1): Out-of-bounds read (OVERRUN)
3. overrun-local: Overrunning array base_adr of 7 4-byte elements at
element index 7 (byte offset 28) using index bus (which evaluates to 7).
Change-Id: I7caec60298cf27bd669796e0e05e4a896f92befd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12781
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Switching on DQS Gate Early and DQS Gate Extension with
500R DQS/DSQN Resistors. This setup was recommended by
Synopsys.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
root_port_init_config() pcie.c wasn't initializing a variable before
passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the
uninitialized value into a register.
In theory, the register would only be used if data was being written,
and pch_iobp_exec() was being used to read the data, not write it, so
this change shouldn't have any practical effect.
Fixes coverity error:
CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT)
Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12778
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Implement system reset by calling the watchdog soft reset.
Following the soft reset, the SoC will reset to the same logic
state and therefore have the same effect as a hard (power-on)
reset except for:
- watchdog scratch registers will be unaffected (hard reset
will clear them)
- the real time clock will be unaffected
BUG=none
TEST=tested on Pistachio bring up board
Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12755
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Verified boot needs hard_reset() now, so offer a dummy implementation
for the Imagination chip. Sorry, I don't have the specs for this chip
anymore to make a real implementation, but I would like to keep this
code from bit rotting.
Change-Id: I15aa47f7d248b99901a2ac0e65a46b43d7718717
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12723
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.
Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The macro PCI_DEV_PIRQ_ROUTE ends with a comma and escaped newline.
Ending a macro with an escaped newline is always wrong.
The final comma is not necessary, as all uses of PCI_DEV_PIRQ_ROUTE()
properly separate calls with a comma.
I haven't investigated whether this is causing a real issue, but it should
be leaving gaps in struct baytrail_irq_route.pcidev.
The non-FSP baytrail does not have this issue.
Change-Id: If6782176068b07cb3bc819c00d1cdb1b618bcea8
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Implement hard_reset() as power_reset() to make
vboot happy.
Change-Id: I16831055bd6ba8a8c95836fcf31f29c068153fcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12722
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
On Skylake systems, the bootblock fails to compile with the following
error message:
bootblock_simple.c:6.1:
0x13930e0 copy Internal compiler error: non dominated rhs use point
0x13a3f70?
Aborted (core dumped)
The option -fno-simplify-phi works around the issue, but will cause the
code to use more registers, hence we also need to enable -mcpu=p4 (see
intel/truxton mainboard for another example of where this has been done
in the past)
Change-Id: Iea1a1ba18d76c7323bb626c5f4b0032e4ee04a86
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12719
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The ALIGN_CURRENT macro relied on a local variable name
as well as being defined in numerous compilation units.
Replace those instances with an acpi_align_current()
inline function.
Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12707
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to allow for updateable memory init code on intel x86
platforms one needs to ensure the saved mrc data matches the code
consuming the data. To that end add a version field to the saved
data structure.
BUG=chrome-os-partner:46050
BRANCH=None
TEST=Built and booted on glados. Suspended and resumed. Also verified
version mismatch path.
Change-Id: Ie86db1750af5d9bff6446999b0d04b60612f8d29
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12700
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Don't select SPI_ATOMIC_SEQUENCING unless SPI_FLASH is being used.
warning: (... SOC_MEDIATEK_MT8173) selects SPI_ATOMIC_SEQUENCING
which has unmet direct dependencies (SPI_FLASH)
Change-Id: I93e9a7102d1d0ef62565110b5b3b677da8d0c72b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12657
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
According to the ACPI Spec for CondRefOf, the result argument is
optional. In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL. Since it's
an optional argument, just remove it.
dsdt.aml 640: If (CondRefOf (^GBUF, Local0)) {
Warning 3144 - Method Local is set but never used ^ (Local0)
Change-Id: Ie2f46808e92c309a63ba7661bcbd77402a08366a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12694
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The BBAR register (BIOS Base Address Configuration Register) defined in
the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet.
Accessing it seems harmless, but should likely be avoided.
Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12671
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that only CBFS access is supported for finding resources
within the boot media the assets infrastructure can be removed.
Remove it.
BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.
Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The USE_FMAP Kconfig symbol doesn't exist, so remove things that are
depending on it not being enabled.
Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12663
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit
66e0c4c8 (cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS)
Both CPU_MICROCODE_IN_CBFS and SUPPORT_CPU_UCODE_IN_CBFS were present,
so just remove CPU_MICROCODE_IN_CBFS.
SMM_MODULES was removed in
commit 44cbe10f (smm: Merge configs SMM_MODULES and SMM_TSEG)
Change-Id: Icdd4fcc5a3a97aee443742aaab3df92b53ff4589
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12662
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In coreboot, bool, hex, and int type symbols are ALWAYS defined.
Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12560
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=chromeos-2015.07
BUG=none
TEST=verified on Oak rev3
Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f
Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297224
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
