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coreboot-kgpe-d16/util/amdfwtool/amdfwtool.c

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util/: Replace GPLv2 boiler plate with SPDX header Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|This[\s*]*program[\s*]*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.*[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*This[\s*#]*program[\s*#]*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.*[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: I1008a63b804f355a916221ac994701d7584f60ff Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08 20:48:04 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
/*
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* ROMSIG At ROMBASE + 0x[0,2,4,8]20000:
amdfwtool: Postpone the usage of PSP combo directory If we only need to "combo" two PSP directories into one image, we can put first address in romsig 0x10 and second one in romsig 0x14. If we really need to put three, the 0x14 is the combo directory which points to multiple level-2 PSP directories. I guess that two PSP can also use combo directory, with only one level-2 directory. But nobody seems to do that. Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 06:47:31 +01:00
* 0 4 8 C
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
* +------------+---------------+----------------+------------+
* | 0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
* +------------+---------------+----------------+------------+
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* | PSPDIR ADDR|PSPDIR ADDR(C) | BDT ADDR 0 | BDT ADDR 1 |
* +------------+---------------+----------------+------------+
* | BDT ADDR 2 | | BDT ADDR 3(C) | |
* +------------+---------------+----------------+------------+
* (C): Could be a combo header
*
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
* EC ROM should be 64K aligned.
*
amdfwtool: Correct the PSP2 directory layout PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 05:29:04 +01:00
* PSP directory (Where "PSPDIR ADDR" points)
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
* +------------+---------------+----------------+------------+
* | 'PSP$' | Fletcher | Count | Reserved |
* +------------+---------------+----------------+------------+
* | 0 | size | Base address | Reserved | Pubkey
* +------------+---------------+----------------+------------+
* | 1 | size | Base address | Reserved | Bootloader
* +------------+---------------+----------------+------------+
* | 8 | size | Base address | Reserved | Smu Firmware
* +------------+---------------+----------------+------------+
* | 3 | size | Base address | Reserved | Recovery Firmware
* +------------+---------------+----------------+------------+
* | |
* | |
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* | Other PSP Firmware |
* | |
* +------------+---------------+----------------+------------+
* | 40 | size | Base address | Reserved |---+
* +------------+---------------+----------------+------------+ |
* :or 48(A/B A): size : Base address : Reserved : |
* + - - + - - + - - + - - + |
* : 4A(A/B B): size : Base address : Reserved : |
* +------------+---------------+----------------+------------+ |
* (A/B A) & (A/B B): Similar as 40, pointing to PSP level 2 |
* for A/B recovery |
* |
* |
* +------------+---------------+----------------+------------+ |
* | '2LP$' | Fletcher | Count | Reserved |<--+
* +------------+---------------+----------------+------------+
* | |
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
* | |
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* | PSP Firmware |
* | (2nd-level is not required on all families) |
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
* | |
* +------------+---------------+----------------+------------+
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* BIOS Directory Table (BDT) is similar
amdfwtool: Correct the PSP2 directory layout PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 05:29:04 +01:00
*
amdfwtool: Postpone the usage of PSP combo directory If we only need to "combo" two PSP directories into one image, we can put first address in romsig 0x10 and second one in romsig 0x14. If we really need to put three, the 0x14 is the combo directory which points to multiple level-2 PSP directories. I guess that two PSP can also use combo directory, with only one level-2 directory. But nobody seems to do that. Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 06:47:31 +01:00
* PSP Combo directory
amdfwtool: Correct the PSP2 directory layout PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 05:29:04 +01:00
* +------------+---------------+----------------+------------+
amdfwtool: Fix some fields in PSP level-2 directory Change-Id: Ib2da7f2210a823fce7f05824e2a2b73d3c0490e9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 06:34:59 +01:00
* | 'PSP2' | Fletcher | Count |Look up mode|
amdfwtool: Correct the PSP2 directory layout PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 05:29:04 +01:00
* +------------+---------------+----------------+------------+
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
* | R e s e r v e d |
* +------------+---------------+----------------+------------+
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* | ID-Sel | PSP ID | PSPDIR ADDR | | 1st PSP directory
amdfwtool: Correct the PSP2 directory layout PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 05:29:04 +01:00
* +------------+---------------+----------------+------------+
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory
amdfwtool: Correct the PSP2 directory layout PSP2 is for Combo BIOS, which is the idea that one image supports 2 kinds of APU. The PSP2 feature is for the future, not for current products. The newest document about PSP2 is not available. I made it from the draft code I made when I was in AMD. Change-Id: I65328db197c02ee67f3e99faf4ab8acabd339657 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/12474 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 05:29:04 +01:00
* +------------+---------------+----------------+------------+
* | |
* | Other PSP |
* | |
* +------------+---------------+----------------+------------+
amdfwtool: Update and extend PSP header format description The comment in the header amdfwtool.c was written long time ago and is needed to get updated. Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2021-10-14 10:14:09 +02:00
* BDT Combo is similar
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
*/
util/amdfwtool/amdfwtool: Don't rewrite macros Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 09:58:29 +02:00
#include <commonlib/bsd/helpers.h>
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
#include <fcntl.h>
#include <errno.h>
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
#include <limits.h>
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
#include <openssl/sha.h>
util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-07 22:16:39 +02:00
#include <stdbool.h>
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
#include <stdio.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
#include <string.h>
#include <stdlib.h>
#include <getopt.h>
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
#include <libgen.h>
util/amdfwtool: portability fixes for FreeBSD Add the stdint.h header, and drop the GLIBC section from amdfwtool.h to build this tool on FreeBSD as well as Linux. Signed-off-by: Idwer Vollering <vidwer@gmail.com> Change-Id: I295fd308b0f5e2902931f02c9455823a614976de Reviewed-on: https://review.coreboot.org/c/coreboot/+/48977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30 00:01:59 +01:00
#include <stdint.h>
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
#include "amdfwtool.h"
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
#define AMD_ROMSIG_OFFSET 0x20000
#define MIN_ROM_KB 256
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Align PSP NVRAM Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-11 17:44:43 +02:00
#define _MAX(A, B) (((A) > (B)) ? (A) : (B))
#define ERASE_ALIGNMENT 0x1000U
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
#define TABLE_ALIGNMENT 0x1000U
#define BLOB_ALIGNMENT 0x100U
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT)
util/amdfwtool: Align PSP NVRAM Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-11 17:44:43 +02:00
#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT)
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Add argument for soft fuse override Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:16:41 +02:00
#define DEFAULT_SOFT_FUSE_CHAIN "0x1"
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
/* Defines related to hashing signed binaries */
enum hash_header_ver {
HASH_HDR_V1 = 1,
};
/* Signature ID enums are defined by PSP based on the algorithm used. */
enum signature_id {
SIG_ID_RSA2048,
SIG_ID_RSA4096 = 2,
};
#define HASH_FILE_SUFFIX ".hash"
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
#define EFS_FILE_SUFFIX ".efs"
#define TMP_FILE_SUFFIX ".tmp"
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
#define BODY_FILE_SUFFIX ".body"
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
/*
util/amdfwtool: Remove duplicate PSP2 support There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:50:37 +01:00
* Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP
* can support an optional "combo" implementation. If the PSP sees the
* PSP2 cookie, it interprets the table as a roadmap to additional PSP
* tables. Using this, support for multiple product generations may be
* built into one image. If the PSP$ cookie is found, the table is a
* normal directory table.
*
* Modern generations supporting the combo directories require the
* pointer to be at offset 0x14 of the Embedded Firmware Structure,
amdfwtool: Remove the hints of flag --combo-capable A few references to "--combo-capable" were left after commit 4bfb36ed68154d8ee6fc77a6b2bf79938cae9e8a Change-Id: I6f425db2a8b86d7ad928baee6bc7b07e5190ba37 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73281 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-26 05:31:31 +01:00
* regardless of the type of directory used. The --use-combo
util/amdfwtool: Remove duplicate PSP2 support There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:50:37 +01:00
* argument enforces this placement.
*
* TODO: Future work may require fully implementing the PSP_COMBO feature.
amdfwtool: Postpone the usage of PSP combo directory If we only need to "combo" two PSP directories into one image, we can put first address in romsig 0x10 and second one in romsig 0x14. If we really need to put three, the 0x14 is the combo directory which points to multiple level-2 PSP directories. I guess that two PSP can also use combo directory, with only one level-2 directory. But nobody seems to do that. Change-Id: Ic450a846bc04db90a75cd417b6d7104fe2a5b177 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13739 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 06:47:31 +01:00
*/
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
/*
* Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3.
* The checksum field of the passed PDU does not need to be reset to zero.
*
* The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of
* Lawrence Livermore Labs. The Fletcher Checksum was proposed as an
* alternative to cyclical redundancy checks because it provides error-
* detection properties similar to cyclical redundancy checks but at the
* cost of a simple summation technique. Its characteristics were first
* published in IEEE Transactions on Communications in January 1982. One
* version has been adopted by ISO for use in the class-4 transport layer
* of the network protocol.
*
* This program expects:
* stdin: The input file to compute a checksum for. The input file
* not be longer than 256 bytes.
* stdout: Copied from the input file with the Fletcher's Checksum
* inserted 8 bytes after the beginning of the file.
* stderr: Used to print out error messages.
*/
util/amdfwtool: Clarify call to fletcher32 The fletcher32 algorithm generates a sum over a range of 16-bit WORDs. Change the function's interface to be more generic, accepting a more intuitive size in BYTEs. Don't require the caller to understand the nature of the algorithm and convert to WORDs prior to calling. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 15:18:44 +01:00
static uint32_t fletcher32(const void *data, int length)
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
{
uint32_t c0;
uint32_t c1;
uint32_t checksum;
int index;
util/amdfwtool: Clarify call to fletcher32 The fletcher32 algorithm generates a sum over a range of 16-bit WORDs. Change the function's interface to be more generic, accepting a more intuitive size in BYTEs. Don't require the caller to understand the nature of the algorithm and convert to WORDs prior to calling. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 15:18:44 +01:00
const uint16_t *pptr = data;
length /= 2;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
c0 = 0xFFFF;
c1 = 0xFFFF;
util/amdfwtool: Correct fletcher32 algorithm Change the fletcher32 checksum calculation to match PSP and AGESA implementations. The symptom of the failure has only been noted in Picasso's BIOS Directory Table, when a BIOS binary image of different sizes were passed to amdfwtool. The PSP halts the boot process with the bad BDT checksum, and if allowed to continue, AGESA asserts later due to a failed BDT verification. This version has been verified to produce the same result as found at https://en.wikipedia.org/wiki/Fletcher%27s_checksum. TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom is unchanged. Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-23 15:24:30 +02:00
while (length) {
index = length >= 359 ? 359 : length;
length -= index;
amdfwtool: Fix indentation Change-Id: I4c57c9bade318d54315f9692cd37edb694e33aa9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58320 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-14 10:15:11 +02:00
do {
c0 += *(pptr++);
c1 += c0;
} while (--index);
util/amdfwtool: Correct fletcher32 algorithm Change the fletcher32 checksum calculation to match PSP and AGESA implementations. The symptom of the failure has only been noted in Picasso's BIOS Directory Table, when a BIOS binary image of different sizes were passed to amdfwtool. The PSP halts the boot process with the bad BDT checksum, and if allowed to continue, AGESA asserts later due to a failed BDT verification. This version has been verified to produce the same result as found at https://en.wikipedia.org/wiki/Fletcher%27s_checksum. TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom is unchanged. Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-23 15:24:30 +02:00
c0 = (c0 & 0xFFFF) + (c0 >> 16);
c1 = (c1 & 0xFFFF) + (c1 >> 16);
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}
util/amdfwtool: Clarify call to fletcher32 The fletcher32 algorithm generates a sum over a range of 16-bit WORDs. Change the function's interface to be more generic, accepting a more intuitive size in BYTEs. Don't require the caller to understand the nature of the algorithm and convert to WORDs prior to calling. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 15:18:44 +01:00
/* Sums[0,1] mod 64K + overflow */
c0 = (c0 & 0xFFFF) + (c0 >> 16);
c1 = (c1 & 0xFFFF) + (c1 >> 16);
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
checksum = (c1 << 16) | c0;
return checksum;
}
util/amdfwtool: fix clang warnings Various fixes for clang warnings: warning: arithmetic on a pointer to void is a GNU extension - change *rom from void* to char* and cast back to void* as needed warning: implicit conversion changes signedness - In ALIGN macro, pass in value as unsigned warning: no previous prototype for function - Change functions to static warning: no previous extern declaration for non-static variable - Change global variables to static warning: comparison of integers of different signs - Make loop variable 'i' unsigned warning: variable 'output' may be uninitialized - Make sure an output filename was specified warning: implicit conversion loses integer precision - cast fd_stat.st_size to the appropriate type Change-Id: I0134a79c00938e121e63b52fd63bd502f4cb9e99 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17322 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 18:44:18 +01:00
static void usage(void)
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
{
util/amdfwtool: add usage text Change-Id: I0ddb4516c03b0240d9134b35753ad901932d3f53 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17323 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 18:37:53 +01:00
printf("amdfwtool: Create AMD Firmware combination\n");
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
printf("Usage: amdfwtool [options] --flashsize <size> --output <filename>\n");
printf("--xhci <FILE> Add XHCI blob\n");
printf("--imc <FILE> Add IMC blob\n");
printf("--gec <FILE> Add GEC blob\n");
util/amdfwtool: add usage text Change-Id: I0ddb4516c03b0240d9134b35753ad901932d3f53 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17323 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 18:37:53 +01:00
printf("\nPSP options:\n");
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
printf("--use-combo Use the COMBO layout\n");
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
printf("--multilevel Generate primary and secondary tables\n");
printf("--nvram <FILE> Add nvram binary\n");
printf("--soft-fuse Set soft fuse\n");
printf("--token-unlock Set token unlock\n");
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
printf("--nvram-base <HEX_VAL> Base address of nvram\n");
printf("--nvram-size <HEX_VAL> Size of nvram\n");
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
printf("--whitelist Set if there is a whitelist\n");
printf("--use-pspsecureos Set if psp secure OS is needed\n");
printf("--load-mp2-fw Set if load MP2 firmware\n");
printf("--load-s0i3 Set if load s0i3 firmware\n");
printf("--verstage <FILE> Add verstage\n");
printf("--verstage_sig Add verstage signature\n");
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
printf("--recovery-ab Use the recovery A/B layout\n");
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
printf("\nBIOS options:\n");
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
printf("--instance <number> Sets instance field for the next BIOS\n");
amdfwtool: Cleanup the message of help 1. Wrap the long lines. 2. Align the message. 3. Add new SOC name, Cezanne. 4. Fix the cases. Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-27 11:19:43 +02:00
printf(" firmware\n");
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
printf("--apcb <FILE> Add AGESA PSP customization block\n");
printf("--apob-base <HEX_VAL> Destination for AGESA PSP output block\n");
printf("--apob-nv-base <HEX_VAL> Location of S3 resume data\n");
printf("--apob-nv-size <HEX_VAL> Size of S3 resume data\n");
printf("--ucode <FILE> Add microcode patch\n");
printf("--bios-bin <FILE> Add compressed image; auto source address\n");
printf("--bios-bin-src <HEX_VAL> Address in flash of source if -V not used\n");
printf("--bios-bin-dest <HEX_VAL> Destination for uncompressed BIOS\n");
printf("--bios-uncomp-size <HEX> Uncompressed size of BIOS image\n");
printf("--output <filename> output filename\n");
printf("--flashsize <HEX_VAL> ROM size in bytes\n");
util/amdfwtool: Add fanless SMU firmware options The Stoney Ridge program has OPNs that are considered fanless. These APUs are strapped to search for unique SMU firmware, indicated by Type[8]=1 in the directory table entry. Add new options to amdfwtool and include the blobs in the build with the appropriate bit set in the Type encoding. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da) Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18991 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-17 23:30:51 +01:00
printf(" size must be larger than %dKB\n",
util/amdfwtool: add usage text Change-Id: I0ddb4516c03b0240d9134b35753ad901932d3f53 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17323 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 18:37:53 +01:00
MIN_ROM_KB);
util/amdfwtool: Add fanless SMU firmware options The Stoney Ridge program has OPNs that are considered fanless. These APUs are strapped to search for unique SMU firmware, indicated by Type[8]=1 in the directory table entry. Add new options to amdfwtool and include the blobs in the build with the appropriate bit set in the Type encoding. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da) Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18991 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-17 23:30:51 +01:00
printf(" and must a multiple of 1024\n");
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
printf("--location Location of Directory\n");
printf("--anywhere Use any 64-byte aligned addr for Directory\n");
printf("--sharedmem Location of PSP/FW shared memory\n");
printf("--sharedmem-size Maximum size of the PSP/FW shared memory\n");
amdfwtool: Cleanup the message of help 1. Wrap the long lines. 2. Align the message. 3. Add new SOC name, Cezanne. 4. Fix the cases. Change-Id: Id537d7c9b77641289274c1b2b6f606e2be37ac6b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-27 11:19:43 +02:00
printf(" area\n");
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
printf("\nEmbedded Firmware Structure options used by the PSP:\n");
printf("--spi-speed <HEX_VAL> SPI fast speed to place in EFS Table\n");
printf(" 0x0 66.66Mhz\n");
printf(" 0x1 33.33MHz\n");
printf(" 0x2 22.22MHz\n");
printf(" 0x3 16.66MHz\n");
printf(" 0x4 100MHz\n");
printf(" 0x5 800KHz\n");
printf("--spi-read-mode <HEX_VAL> SPI read mode to place in EFS Table\n");
printf(" 0x0 Normal Read (up to 33M)\n");
printf(" 0x1 Reserved\n");
printf(" 0x2 Dual IO (1-1-2)\n");
printf(" 0x3 Quad IO (1-1-4)\n");
printf(" 0x4 Dual IO (1-2-2)\n");
printf(" 0x5 Quad IO (1-4-4)\n");
printf(" 0x6 Normal Read (up to 66M)\n");
printf(" 0x7 Fast Read\n");
printf("--spi-micron-flag <HEX_VAL> Micron SPI part support for RV and later SOC\n");
printf(" 0x0 Micron parts are not used\n");
printf(" 0x1 Micron parts are always used\n");
printf(" 0x2 Micron parts optional, this option is only\n");
printf(" supported with RN/LCN SOC\n");
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
printf("\nGeneral options:\n");
printf("-c|--config <config file> Config file\n");
printf("-d|--debug Print debug message\n");
printf("-l|--list List out the firmware files\n");
printf("-h|--help Show this help\n");
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
amd_fw_entry amd_psp_fw_table[] = {
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
{ .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
amdfwtool: Change the some FW's level for A/B recovery The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to level 2 only for A/B recovery for Sabrina, which is going to be the long term and A/B recovery layout only. So the amdfwtool should be changed for Sabrina. The old levels of these 3 FWs are for Cezanne, which doesn't use AB recovery now. Just set the specific field levels in generic Cezanne folder for demo. Leave the fw.cfg in Guybrush unchanged. Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-24 08:15:50 +01:00
{ .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH },
{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
{ .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 | PSP_LVL2_AB,
.skip_hashing = true },
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
{ .type = AMD_FW_ABL_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
{ .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_SOC_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_DEBUG_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_INTERFACE_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add HW IPCFG file whose subprog is 1 And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-07 12:48:11 +01:00
{ .type = AMD_HW_IPCFG, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_HW_IPCFG, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
{ .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_SEC_GASKET, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_MP2_FW, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_MP2_FW, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_MP2_FW, .subprog = 2, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_DRIVER_ENTRIES, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_KVM_IMAGE, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
{ .type = AMD_FW_MP5, .subprog = 0, .level = PSP_BOTH | PSP_BOTH_AB },
{ .type = AMD_FW_MP5, .subprog = 1, .level = PSP_BOTH | PSP_BOTH_AB },
{ .type = AMD_FW_MP5, .subprog = 2, .level = PSP_BOTH | PSP_BOTH_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_S0I3_DRIVER, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_ABL1, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_ABL2, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_ABL3, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_ABL4, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_ABL5, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_ABL6, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_ABL7, .level = PSP_BOTH | PSP_LVL2_AB },
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
{ .type = AMD_SEV_DATA, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_SEV_CODE, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_FW_PSP_WHITELIST, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_VBIOS_BTLOADER, .level = PSP_BOTH | PSP_LVL2_AB },
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
{ .type = AMD_FW_DXIO, .level = PSP_BOTH | PSP_BOTH_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_USB_PHY, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_FW_TOS_SEC_POLICY, .level = PSP_BOTH | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_DRTM_TA, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_KEYDB_BL, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_FW_KEYDB_TOS, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_FW_PSP_VERSTAGE, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_FW_VERSTAGE_SIG, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-24 02:04:51 +01:00
{ .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: move FW_MPIO to PSP Dir Level 2 where it belongs Type 0x5d (MPIO Firmware) was mistakenly placed to PSP Level 1 directory. It should be in Level 2 PSP directory instead. Change-Id: Ic5ea00859f1055e0c91600c5f941c5d3acca36e2 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bao Zheng <fishbaozi@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-07 22:09:09 +01:00
{ .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
{ .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB },
util/amdfwutil: Order enum and use hex consistently This makes it easier to match the code to the datasheet (55758, NDA only). This also removes the duplicate lines: "{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }," TESTED: google/vilboz still boots. Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-09-30 08:33:28 +02:00
{ .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{ .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Add entry RIB whose subprog equals 1 For the PHX, it uses subprog 0. For the PHX2, it uses subprog 1. Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-30 06:52:30 +01:00
{ .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
{ .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB },
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
{ .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
util/amdfwtool: Add new types These are used on newer platforms. Change-Id: I20dc77fb6f83dc813e3da5fe30f8f52068fc4662 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-10-04 17:50:21 +02:00
{ .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB },
{ .type = AMD_FW_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB },
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
{ .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true },
{ .type = AMD_FW_MPCCX, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB },
{ .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB },
{ .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB },
util/amdfwtool: Add UMSMU blob support Add PSP blob Type 0xA2 uMsmu support. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ib38ec03bf20f46774f7438b21d18704cc1ec57fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-07 18:12:40 +01:00
{ .type = AMD_FW_UMSMU, .level = PSP_LVL2 | PSP_LVL2_AB },
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
{ .type = AMD_FW_INVALID },
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
};
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
amd_fw_entry amd_fw_table[] = {
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
{ .type = AMD_FW_XHCI },
{ .type = AMD_FW_IMC },
{ .type = AMD_FW_GEC },
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
{ .type = AMD_FW_INVALID },
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
};
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
amd_bios_entry amd_bios_table[] = {
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
{ .type = AMD_BIOS_RTM_PUBKEY, .inst = 0, .level = BDT_BOTH },
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
{ .type = AMD_BIOS_SIG, .inst = 0, .level = BDT_BOTH },
util/amdfwtool: Add holding locations for more APCBs Increase the number of potential APCB images to 5 by adding to the amd_bios_table. New instance IDs are from 0 to 4. The backup APCB block (type 0x68) still supports only instance ID 0. Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-25 19:03:53 +02:00
{ .type = AMD_BIOS_APCB, .inst = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 2, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 3, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 4, .level = BDT_BOTH },
amdfwtool: Allow for up to 16 APCB entries Increase the number of allowed APCB entries in amdfwtool. BUG=b:150455865 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238 Reviewed-on: https://chromium-review.googlesource.com/2084944 Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03 18:35:02 +01:00
{ .type = AMD_BIOS_APCB, .inst = 5, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 6, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 7, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 8, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 9, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 10, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 11, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 12, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 13, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 14, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB, .inst = 15, .level = BDT_BOTH },
util/amdfwtool: Add instances for APCB backup Match each of the possible APCB items with a corresponding backup APCB. A missing backup copy can prevent the system from booting. Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-04 01:57:48 +01:00
{ .type = AMD_BIOS_APCB_BK, .inst = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 2, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 3, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 4, .level = BDT_BOTH },
amdfwtool: Allow for up to 16 APCB entries Increase the number of allowed APCB entries in amdfwtool. BUG=b:150455865 TEST=Boot Trembyle BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ibdd2f2b9766735bc9aba98b5216e589b6cace238 Reviewed-on: https://chromium-review.googlesource.com/2084944 Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39861 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03 18:35:02 +01:00
{ .type = AMD_BIOS_APCB_BK, .inst = 5, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 6, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 7, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 8, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 9, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 10, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 11, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 12, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 13, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 14, .level = BDT_BOTH },
{ .type = AMD_BIOS_APCB_BK, .inst = 15, .level = BDT_BOTH },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_APOB, .level = BDT_BOTH },
{ .type = AMD_BIOS_BIN,
amdfwtool: Add instance = 0 for bios image For future BIOS image entry whose instance = 1. Change-Id: Iaa40872b270cf9ff289794c8c51c4d8b448d862d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-10-16 14:34:57 +02:00
.reset = 1, .copy = 1, .zlib = 1, .inst = 0, .level = BDT_BOTH },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_APOB_NV, .level = BDT_LVL2 },
{ .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 0, .level = BDT_BOTH },
amdfwtool: Add entries for PMUI & PMUD with instance 2 Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-17 10:22:15 +01:00
{ .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 0, .level = BDT_BOTH },
util/amdfwtool: Add more instances some types in BDT Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04 20:37:10 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 0, .level = BDT_BOTH },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH },
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 0, .level = BDT_BOTH },
util/amdfwtool: Add more instances some types in BDT Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04 20:37:10 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 0, .level = BDT_BOTH },
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 0, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 0, .level = BDT_BOTH },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH },
amdfwtool: Add entries for PMUI & PMUD with instance 2 Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-17 10:22:15 +01:00
{ .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 2, .subpr = 1, .level = BDT_BOTH },
util/amdfwtool: Add more instances some types in BDT Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04 20:37:10 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 3, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 1, .level = BDT_BOTH },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH },
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 1, .level = BDT_BOTH },
util/amdfwtool: Add more instances some types in BDT Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04 20:37:10 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 1, .level = BDT_BOTH },
amdfwtool: Add entry types required to support glinda & phoenix SOC Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:29:03 +02:00
{ .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 1, .level = BDT_BOTH },
{ .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 1, .level = BDT_BOTH },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 },
{ .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 },
{ .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 },
util/amdfwtool: Add more instances some types in BDT Some hardware uses more instances. Change-Id: Ie4ed2ce0d077013b450df99a88e904c8658cfc2d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68121 Reviewed-by: Marvin Drees <marvin.drees@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04 20:37:10 +02:00
{ .type = AMD_BIOS_UCODE, .inst = 3, .level = BDT_LVL2 },
{ .type = AMD_BIOS_UCODE, .inst = 4, .level = BDT_LVL2 },
{ .type = AMD_BIOS_UCODE, .inst = 5, .level = BDT_LVL2 },
{ .type = AMD_BIOS_UCODE, .inst = 6, .level = BDT_LVL2 },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_MP2_CFG, .level = BDT_LVL2 },
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
{ .type = AMD_BIOS_PSP_SHARED_MEM, .inst = 0, .level = BDT_BOTH },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{ .type = AMD_BIOS_INVALID },
};
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
typedef struct _context {
char *rom; /* target buffer, size of flash device */
uint32_t rom_size; /* size of flash device */
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
uint32_t address_mode; /* 0:abs address; 1:relative to flash; 2: relative to table */
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
uint32_t current; /* pointer within flash & proxy buffer */
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
uint32_t current_pointer_saved;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
uint32_t current_table;
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
} context;
#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
#define RUN_OFFSET_MODE(ctx, offset, mode) \
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
((mode) == AMD_ADDR_PHYSICAL ? RUN_BASE(ctx) + (offset) : \
((mode) == AMD_ADDR_REL_BIOS ? (offset) : \
amdfwtool: Add missing parentheses in macro definition Change-Id: I1b43dbb8cdc748960f25d7b0629aa81528a2a476 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-21 03:43:08 +01:00
((mode) == AMD_ADDR_REL_TAB ? (offset) - (ctx).current_table : (offset))))
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
#define RUN_OFFSET(ctx, offset) RUN_OFFSET_MODE((ctx), (offset), (ctx).address_mode)
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
#define RUN_TO_OFFSET(ctx, run) ((ctx).address_mode == AMD_ADDR_PHYSICAL ? \
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
(run) - RUN_BASE(ctx) : (run)) /* TODO: */
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
#define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
/* The mode in entry can not be higher than the header's.
For example, if table mode is 0, all the entry mode will be 0. */
#define RUN_CURRENT_MODE(ctx, mode) RUN_OFFSET_MODE((ctx), (ctx).current, \
(ctx).address_mode < (mode) ? (ctx).address_mode : (mode))
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
#define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))
#define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current)
#define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom))
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
#define BUFF_TO_RUN_MODE(ctx, ptr, mode) RUN_OFFSET_MODE((ctx), ((char *)(ptr) - (ctx).rom), \
(ctx).address_mode < (mode) ? (ctx).address_mode : (mode))
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
#define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current)
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
/* Only set the address mode in entry if the table is mode 2. */
#define SET_ADDR_MODE(table, mode) \
((table)->header.additional_info_fields.address_mode == \
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
AMD_ADDR_REL_TAB ? (mode) : 0)
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
#define SET_ADDR_MODE_BY_TABLE(table) \
SET_ADDR_MODE((table), (table)->header.additional_info_fields.address_mode)
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
static void free_psp_firmware_filenames(amd_fw_entry *fw_table)
{
amd_fw_entry *index;
for (index = fw_table; index->type != AMD_FW_INVALID; index++) {
if (index->filename &&
index->type != AMD_FW_VERSTAGE_SIG &&
index->type != AMD_FW_PSP_VERSTAGE &&
index->type != AMD_FW_SPL &&
index->type != AMD_FW_PSP_WHITELIST) {
free(index->filename);
index->filename = NULL;
}
}
}
static void free_bdt_firmware_filenames(amd_bios_entry *fw_table)
{
amd_bios_entry *index;
for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) {
if (index->filename &&
index->type != AMD_BIOS_APCB &&
index->type != AMD_BIOS_BIN &&
index->type != AMD_BIOS_APCB_BK &&
index->type != AMD_BIOS_UCODE) {
free(index->filename);
index->filename = NULL;
}
}
}
static void amdfwtool_cleanup(context *ctx)
{
free(ctx->rom);
ctx->rom = NULL;
/* Free the filename. */
free_psp_firmware_filenames(amd_psp_fw_table);
free_bdt_firmware_filenames(amd_bios_table);
}
amdfwtool: Pack out-of-bounds check into a function and move Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 06:09:07 +02:00
void assert_fw_entry(uint32_t count, uint32_t max, context *ctx)
{
if (count >= max) {
fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items "
"(%d)\n", count, max);
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
amdfwtool: Pack out-of-bounds check into a function and move Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 06:09:07 +02:00
exit(1);
}
}
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
static void set_current_pointer(context *ctx, uint32_t value)
{
if (ctx->current_pointer_saved != 0xFFFFFFFF &&
ctx->current_pointer_saved != ctx->current) {
fprintf(stderr, "Error: The pointer is changed elsewhere\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
exit(1);
}
ctx->current = value;
if (ctx->current > ctx->rom_size) {
fprintf(stderr, "Error: Packing data causes overflow\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
exit(1);
}
ctx->current_pointer_saved = ctx->current;
}
static void adjust_current_pointer(context *ctx, uint32_t add, uint32_t align)
{
/* Get */
set_current_pointer(ctx, ALIGN_UP(ctx->current + add, align));
}
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
static void *new_psp_dir(context *ctx, int multi)
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
{
void *ptr;
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
/*
* Force both onto boundary when multi. Primary table is after
* updatable table, so alignment ensures primary can stay intact
* if secondary is reprogrammed.
*/
if (multi)
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT);
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
else
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
ptr = BUFF_CURRENT(*ctx);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
((psp_directory_header *)ptr)->num_entries = 0;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
((psp_directory_header *)ptr)->additional_info = 0;
((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx,
sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry),
1);
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
return ptr;
}
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
static void *new_ish_dir(context *ctx)
{
void *ptr;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
ptr = BUFF_CURRENT(*ctx);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, TABLE_ALIGNMENT, 1);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
return ptr;
}
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
static void *new_combo_dir(context *ctx)
{
void *ptr;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
ptr = BUFF_CURRENT(*ctx);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx,
sizeof(psp_combo_header) + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry),
1);
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
return ptr;
}
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie, context *ctx)
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
{
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
psp_combo_directory *cdir = directory;
psp_directory_table *dir = directory;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
bios_directory_table *bdir = directory;
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
uint32_t table_size = 0;
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
if (!count)
return;
amdfwtool: Null check the pointers before using them BUG=b:188769922 Reported-by: Coverity (CID:1438963) Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27 05:26:12 +02:00
if (ctx == NULL || directory == NULL) {
fprintf(stderr, "Calling %s with NULL pointers\n", __func__);
return;
}
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
/* The table size needs to be 0x1000 aligned. So align the end of table. */
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
switch (cookie) {
case PSP2_COOKIE:
amdfwtool: combo: Add combo feature for BIOS table It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-18 09:54:47 +02:00
case BHD2_COOKIE:
util/amdfwtool: Combine table header population Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 00:52:07 +01:00
cdir->header.cookie = cookie;
amdfwtool:combo: Move the filling of field "lookup" into function This filling does not need to be done separately. Change-Id: I53051349923dce40f4fc3f747ab41a93a3798823 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-18 09:26:39 +02:00
/* lookup mode is hardcoded for now. */
cdir->header.lookup = 1;
util/amdfwtool: Combine table header population Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 00:52:07 +01:00
cdir->header.num_entries = count;
cdir->header.reserved[0] = 0;
cdir->header.reserved[1] = 0;
/* checksum everything that comes after the Checksum field */
cdir->header.checksum = fletcher32(&cdir->header.num_entries,
count * sizeof(psp_combo_entry)
+ sizeof(cdir->header.num_entries)
+ sizeof(cdir->header.lookup)
+ 2 * sizeof(cdir->header.reserved[0]));
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
break;
case PSP_COOKIE:
case PSPL2_COOKIE:
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
table_size = ctx->current - ctx->current_table;
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
if ((table_size % TABLE_ALIGNMENT) != 0) {
fprintf(stderr, "The PSP table size should be 4K aligned\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
exit(1);
}
util/amdfwtool: Combine table header population Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 00:52:07 +01:00
dir->header.cookie = cookie;
dir->header.num_entries = count;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
dir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT;
dir->header.additional_info_fields.spi_block_size = 1;
dir->header.additional_info_fields.base_addr = 0;
util/amdfwtool: Combine table header population Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 00:52:07 +01:00
/* checksum everything that comes after the Checksum field */
dir->header.checksum = fletcher32(&dir->header.num_entries,
util/amdfwtool: Clarify call to fletcher32 The fletcher32 algorithm generates a sum over a range of 16-bit WORDs. Change the function's interface to be more generic, accepting a more intuitive size in BYTEs. Don't require the caller to understand the nature of the algorithm and convert to WORDs prior to calling. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 15:18:44 +01:00
count * sizeof(psp_directory_entry)
util/amdfwtool: Combine table header population Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 00:52:07 +01:00
+ sizeof(dir->header.num_entries)
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
+ sizeof(dir->header.additional_info));
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
break;
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
case BHD_COOKIE:
case BHDL2_COOKIE:
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
table_size = ctx->current - ctx->current_table;
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
if ((table_size % TABLE_ALIGNMENT) != 0) {
fprintf(stderr, "The BIOS table size should be 4K aligned\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
exit(1);
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
bdir->header.cookie = cookie;
bdir->header.num_entries = count;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
bdir->header.additional_info_fields.dir_size = table_size / TABLE_ALIGNMENT;
bdir->header.additional_info_fields.spi_block_size = 1;
bdir->header.additional_info_fields.base_addr = 0;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* checksum everything that comes after the Checksum field */
bdir->header.checksum = fletcher32(&bdir->header.num_entries,
count * sizeof(bios_directory_entry)
+ sizeof(bdir->header.num_entries)
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
+ sizeof(bdir->header.additional_info));
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
break;
util/amdfwtool: Combine table header population Rename psp_fill_head() and call it with the cookie to populate the header. The combo header and PSP directory header are similar and should be calculated the same way. Change-Id: I7e634542de65576addadbe683596cbe572de3dcd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 00:52:07 +01:00
}
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}
amdfwtool: Move the filling of table headers into functions It is easier to understand what these statements are about. Change-Id: Ib02c68c9f2ea84020b12682c41fb1a6f8f93d725 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66852 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-11 15:27:49 +01:00
static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdir,
context *ctx, amd_cb_config *cb_config)
{
switch (cb_config->soc_id) {
case PLATFORM_UNKNOWN:
amd_romsig->psp_directory =
BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS);
break;
case PLATFORM_CEZANNE:
case PLATFORM_MENDOCINO:
case PLATFORM_PHOENIX:
case PLATFORM_GLINDA:
case PLATFORM_CARRIZO:
case PLATFORM_STONEYRIDGE:
case PLATFORM_RAVEN:
case PLATFORM_PICASSO:
case PLATFORM_LUCIENNE:
case PLATFORM_RENOIR:
default:
/* for combo, it is also combo_psp_directory */
amd_romsig->new_psp_directory =
BUFF_TO_RUN_MODE(*ctx, pspdir, AMD_ADDR_REL_BIOS);
break;
}
}
static void fill_bios_directory_to_efs(embedded_firmware *amd_romsig, void *biosdir,
context *ctx, amd_cb_config *cb_config)
{
switch (cb_config->soc_id) {
case PLATFORM_RENOIR:
case PLATFORM_LUCIENNE:
case PLATFORM_CEZANNE:
if (!cb_config->recovery_ab)
amd_romsig->bios3_entry =
BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS);
break;
case PLATFORM_MENDOCINO:
case PLATFORM_PHOENIX:
case PLATFORM_GLINDA:
break;
case PLATFORM_CARRIZO:
case PLATFORM_STONEYRIDGE:
case PLATFORM_RAVEN:
case PLATFORM_PICASSO:
default:
amd_romsig->bios1_entry =
BUFF_TO_RUN_MODE(*ctx, biosdir, AMD_ADDR_REL_BIOS);
break;
}
}
util/amdfwtool: Add generic image copy function Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 02:40:49 +01:00
static ssize_t copy_blob(void *dest, const char *src_file, size_t room)
{
int fd;
struct stat fd_stat;
ssize_t bytes;
fd = open(src_file, O_RDONLY);
if (fd < 0) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error opening file: %s: %s\n",
util/amdfwtool: Fix file open error msg Print out the name of the file that failed to open. BUG=none TEST=rerun build-board.sh with missing files BRANCH=none Signed-off-by: Eric Peers <epeers@google.com> Change-Id: Id8543f25ea827fc8764e0315434b834e65bfa7fb Reviewed-on: https://chromium-review.googlesource.com/2090667 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-06 00:04:15 +01:00
src_file, strerror(errno));
util/amdfwtool: Add generic image copy function Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 02:40:49 +01:00
return -1;
}
if (fstat(fd, &fd_stat)) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "fstat error: %s\n", strerror(errno));
util/amdfwtool: Close file descriptor on error Prevents a resource leak. Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-02 18:35:10 +02:00
close(fd);
util/amdfwtool: Add generic image copy function Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 02:40:49 +01:00
return -2;
}
amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-01 10:16:30 +02:00
if ((size_t)fd_stat.st_size > room) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file);
util/amdfwtool: Close file descriptor on error Prevents a resource leak. Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402139 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-02 18:35:10 +02:00
close(fd);
util/amdfwtool: Add generic image copy function Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 02:40:49 +01:00
return -3;
}
bytes = read(fd, dest, (size_t)fd_stat.st_size);
close(fd);
if (bytes != (ssize_t)fd_stat.st_size) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error while reading %s\n", src_file);
util/amdfwtool: Add generic image copy function Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 02:40:49 +01:00
return -4;
}
return bytes;
}
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
static ssize_t read_from_file_to_buf(int fd, void *buf, size_t buf_size)
{
ssize_t bytes;
size_t total_bytes = 0;
do {
bytes = read(fd, buf + total_bytes, buf_size - total_bytes);
if (bytes == 0) {
fprintf(stderr, "Reached EOF probably\n");
break;
}
if (bytes < 0 && errno == EAGAIN)
bytes = 0;
if (bytes < 0) {
fprintf(stderr, "Read failure %s\n", strerror(errno));
return bytes;
}
total_bytes += bytes;
} while (total_bytes < buf_size);
if (total_bytes != buf_size) {
fprintf(stderr, "Read data size(%zu) != buffer size(%zu)\n",
total_bytes, buf_size);
return -1;
}
return buf_size;
}
static ssize_t write_from_buf_to_file(int fd, const void *buf, size_t buf_size)
{
ssize_t bytes;
size_t total_bytes = 0;
do {
bytes = write(fd, buf + total_bytes, buf_size - total_bytes);
if (bytes < 0 && errno == EAGAIN)
bytes = 0;
if (bytes < 0) {
fprintf(stderr, "Write failure %s\n", strerror(errno));
lseek(fd, SEEK_CUR, -total_bytes);
return bytes;
}
total_bytes += bytes;
} while (total_bytes < buf_size);
if (total_bytes != buf_size) {
fprintf(stderr, "Wrote more data(%zu) than buffer size(%zu)\n",
total_bytes, buf_size);
lseek(fd, SEEK_CUR, -total_bytes);
return -1;
}
return buf_size;
}
amdfwtool: Add PSP ID for combo and ISH header for A/B recovery Nobody calls the function until combo or A/B is added, so suppress the warning for now. Test=Majolica (Cezanne) Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-14 09:09:09 +02:00
static uint32_t get_psp_id(enum platform soc_id)
{
uint32_t psp_id;
switch (soc_id) {
case PLATFORM_RAVEN:
case PLATFORM_PICASSO:
psp_id = 0xBC0A0000;
break;
case PLATFORM_RENOIR:
case PLATFORM_LUCIENNE:
psp_id = 0xBC0C0000;
break;
case PLATFORM_CEZANNE:
psp_id = 0xBC0C0140;
break;
case PLATFORM_MENDOCINO:
psp_id = 0xBC0D0900;
break;
case PLATFORM_STONEYRIDGE:
psp_id = 0x10220B00;
break;
amdfwtool: Add missing code for checking new family phoenix & glinda Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:32:43 +02:00
case PLATFORM_GLINDA:
psp_id = 0xBC0E0200;
break;
case PLATFORM_PHOENIX:
psp_id = 0xBC0D0400;
break;
amdfwtool: Add SOC family definition for Carrizo For Carrizo, the soc name was set as UNKNOWN. The change is supposed to be binary unmodified, except the SPI settings. According to the spec, the Stoneyridge and Carrizo have the same definition of SPI setting in EFS. Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-17 05:52:30 +02:00
case PLATFORM_CARRIZO:
amdfwtool: Add PSP ID for combo and ISH header for A/B recovery Nobody calls the function until combo or A/B is added, so suppress the warning for now. Test=Majolica (Cezanne) Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-14 09:09:09 +02:00
default:
psp_id = 0;
break;
}
return psp_id;
}
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
static uint16_t get_psp_fw_type(enum platform soc_id, struct amd_fw_header *header)
{
switch (soc_id) {
case PLATFORM_MENDOCINO:
amdfwtool: Add phoenix and glinda in get_psp_fw_type Change-Id: If80cc5396703cef41cc615008c9f0dac0b7bbb09 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-02-02 02:26:20 +01:00
case PLATFORM_PHOENIX:
case PLATFORM_GLINDA:
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
/* Fallback to fw_type if fw_id is not populated, which serves the same
purpose on older SoCs. */
return header->fw_id ? header->fw_id : header->fw_type;
default:
return header->fw_type;
}
}
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
static int add_single_sha(amd_fw_entry_hash *entry, void *buf, enum platform soc_id)
{
uint8_t hash[SHA384_DIGEST_LENGTH];
struct amd_fw_header *header = (struct amd_fw_header *)buf;
/* Include only signed part for hash calculation. */
size_t len = header->fw_size_signed + sizeof(struct amd_fw_header);
uint8_t *body = (uint8_t *)buf;
if (len > header->size_total)
return -1;
if (header->sig_id == SIG_ID_RSA4096) {
SHA384(body, len, hash);
entry->sha_len = SHA384_DIGEST_LENGTH;
} else if (header->sig_id == SIG_ID_RSA2048) {
SHA256(body, len, hash);
entry->sha_len = SHA256_DIGEST_LENGTH;
} else {
fprintf(stderr, "%s: Unknown signature id: 0x%08x\n",
__func__, header->sig_id);
return -1;
}
memcpy(entry->sha, hash, entry->sha_len);
entry->fw_id = get_psp_fw_type(soc_id, header);
entry->subtype = header->fw_subtype;
return 0;
}
static int get_num_binaries(void *buf, size_t buf_size)
{
struct amd_fw_header *header = (struct amd_fw_header *)buf;
size_t total_len = 0;
int num_binaries = 0;
while (total_len < buf_size) {
num_binaries++;
total_len += header->size_total;
header = (struct amd_fw_header *)(buf + total_len);
}
if (total_len != buf_size) {
fprintf(stderr, "Malformed binary\n");
return -1;
}
return num_binaries;
}
static int add_sha(amd_fw_entry *entry, void *buf, size_t buf_size, enum platform soc_id)
{
struct amd_fw_header *header = (struct amd_fw_header *)buf;
/* Include only signed part for hash calculation. */
size_t total_len = 0;
int num_binaries = get_num_binaries(buf, buf_size);
if (num_binaries <= 0)
return num_binaries;
entry->hash_entries = malloc(num_binaries * sizeof(amd_fw_entry_hash));
if (!entry->hash_entries) {
fprintf(stderr, "Error allocating memory to add FW hash\n");
return -1;
}
entry->num_hash_entries = num_binaries;
/* Iterate through each binary */
for (int i = 0; i < num_binaries; i++) {
if (add_single_sha(&entry->hash_entries[i], buf + total_len, soc_id)) {
free(entry->hash_entries);
return -1;
}
total_len += header->size_total;
header = (struct amd_fw_header *)(buf + total_len);
}
return 0;
}
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
static void integrate_firmwares(context *ctx,
util/amdfwtool: Clarify calculations with structures Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-24 00:42:46 +01:00
embedded_firmware *romsig,
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
amd_fw_entry *fw_table)
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
{
util/amdfwtool/amdfwtool.c: Verify it actually read bytes The function read() returns the number of bytes actually read. Program is assuming it actually read the required number of bytes without checking. This is wrong. This fixes CIDs 1353019 and 1353021 BUG=b:72062481 TEST=Build no errors Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17 18:23:19 +01:00
ssize_t bytes;
amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-01 10:16:30 +02:00
uint32_t i;
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, BLOB_ALIGNMENT);
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Fix whitespace Change-Id: I33e41b745e7ec55ed39d7125fc74b1619d28bb54 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17325 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-08 19:34:02 +01:00
for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
if (fw_table[i].filename != NULL) {
switch (fw_table[i].type) {
case AMD_FW_IMC:
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, 0x10000U);
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
romsig->imc_entry = RUN_CURRENT(*ctx);
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
break;
case AMD_FW_GEC:
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
romsig->gec_entry = RUN_CURRENT(*ctx);
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
break;
case AMD_FW_XHCI:
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
romsig->xhci_entry = RUN_CURRENT(*ctx);
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
break;
default:
/* Error */
break;
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
bytes = copy_blob(BUFF_CURRENT(*ctx),
fw_table[i].filename, BUFF_ROOM(*ctx));
util/amdfwtool: Allow 0-length blobs A side effect of the change 8e0dca05 "util/amdfwtool: Add generic image copy function" was to treat a read operation of zero bytes as a failure. Some implementations exist that use zero length files as a means of removing functionality. This causes amdfwtool to exit with an error. Put the zero length capability back in, and generate the requested table entry with a length field of 0x0. TEST=Boot google/grunt, inspect PSP directory table BUG=b:128507639 Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13 21:43:17 +01:00
if (bytes < 0) {
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool/amdfwtool.c: Verify it actually read bytes The function read() returns the number of bytes actually read. Program is assuming it actually read the required number of bytes without checking. This is wrong. This fixes CIDs 1353019 and 1353021 BUG=b:72062481 TEST=Build no errors Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17 18:23:19 +01:00
exit(1);
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT);
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}
}
amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:39:13 +01:00
/* For debugging */
static void dump_psp_firmwares(amd_fw_entry *fw_table)
{
amd_fw_entry *index;
printf("PSP firmware components:");
for (index = fw_table; index->type != AMD_FW_INVALID; index++) {
if (index->filename)
amdfwtool: Print the entry type when dumping the firmwares Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-25 10:26:55 +02:00
printf(" %2x: %s\n", index->type, index->filename);
amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:39:13 +01:00
}
}
static void dump_bdt_firmwares(amd_bios_entry *fw_table)
{
amd_bios_entry *index;
printf("BIOS Directory Table (BDT) components:");
for (index = fw_table; index->type != AMD_BIOS_INVALID; index++) {
if (index->filename)
amdfwtool: Print the entry type when dumping the firmwares Change-Id: I07bf10e16a42a2b2ab784ee6ac4a4465b7412da6 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-25 10:26:55 +02:00
printf(" %2x: %s\n", index->type, index->filename);
amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:39:13 +01:00
}
}
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
static void write_or_fail(int fd, void *ptr, size_t size)
{
ssize_t written;
written = write_from_buf_to_file(fd, ptr, size);
if (written < 0 || (size_t)written != size) {
fprintf(stderr, "%s: Error writing %zu bytes - written %zd bytes\n",
__func__, size, written);
exit(-1);
}
}
static void write_one_psp_firmware_hash_entry(int fd, amd_fw_entry_hash *entry)
{
uint16_t type = entry->fw_id;
uint16_t subtype = entry->subtype;
write_or_fail(fd, &type, sizeof(type));
write_or_fail(fd, &subtype, sizeof(subtype));
write_or_fail(fd, entry->sha, entry->sha_len);
}
static void write_psp_firmware_hash(const char *filename,
amd_fw_entry *fw_table)
{
struct psp_fw_hash_table hash_header = {0};
int fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, 0666);
if (fd < 0) {
fprintf(stderr, "Error opening file: %s: %s\n",
filename, strerror(errno));
exit(-1);
}
hash_header.version = HASH_HDR_V1;
for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) {
if (fw_table[i].hash_entries[j].sha_len == SHA256_DIGEST_LENGTH) {
hash_header.no_of_entries_256++;
} else if (fw_table[i].hash_entries[j].sha_len ==
SHA384_DIGEST_LENGTH) {
hash_header.no_of_entries_384++;
} else if (fw_table[i].hash_entries[j].sha_len) {
fprintf(stderr, "%s: Error invalid sha_len %d\n",
__func__, fw_table[i].hash_entries[j].sha_len);
exit(-1);
}
}
}
write_or_fail(fd, &hash_header, sizeof(hash_header));
/* Add all the SHA256 hash entries first followed by SHA384 entries. PSP verstage
processes the table in that order. Mixing and matching SHA256 and SHA384 entries
will cause the hash verification failure at run-time. */
for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) {
if (fw_table[i].hash_entries[j].sha_len == SHA256_DIGEST_LENGTH)
write_one_psp_firmware_hash_entry(fd,
&fw_table[i].hash_entries[j]);
}
}
for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
for (unsigned int j = 0; j < fw_table[i].num_hash_entries; j++) {
if (fw_table[i].hash_entries[j].sha_len == SHA384_DIGEST_LENGTH)
write_one_psp_firmware_hash_entry(fd,
&fw_table[i].hash_entries[j]);
}
}
close(fd);
for (unsigned int i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
if (!fw_table[i].num_hash_entries || !fw_table[i].hash_entries)
continue;
free(fw_table[i].hash_entries);
fw_table[i].hash_entries = NULL;
fw_table[i].num_hash_entries = 0;
}
}
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
/**
* process_signed_psp_firmwares() - Process the signed PSP binaries to keep them separate
* @signed_rom: Output file path grouping all the signed PSP binaries.
* @fw_table: Table of all the PSP firmware entries/binaries to be processed.
* @signed_start_addr: Offset of the FMAP section, within the flash device, to hold
* the signed PSP binaries.
* @soc_id: SoC ID of the PSP binaries.
*/
static void process_signed_psp_firmwares(const char *signed_rom,
amd_fw_entry *fw_table,
uint64_t signed_start_addr,
enum platform soc_id)
{
unsigned int i;
int fd;
int signed_rom_fd;
ssize_t bytes, align_bytes;
uint8_t *buf;
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
char *signed_rom_hash;
size_t signed_rom_hash_strlen;
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
struct amd_fw_header header;
struct stat fd_stat;
/* Every blob in amdfw*.rom has to start at address aligned to 0x100. Prepare an
alignment data with 0xff to pad the blobs and meet the alignment requirement. */
uint8_t align_data[BLOB_ALIGNMENT - 1];
memset(align_data, 0xff, sizeof(align_data));
signed_rom_fd = open(signed_rom, O_RDWR | O_CREAT | O_TRUNC,
S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP | S_IROTH | S_IWOTH);
if (signed_rom_fd < 0) {
fprintf(stderr, "Error opening file: %s: %s\n",
signed_rom, strerror(errno));
return;
}
for (i = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
fw_table[i].num_hash_entries = 0;
fw_table[i].hash_entries = NULL;
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
if (!(fw_table[i].filename) || fw_table[i].skip_hashing)
continue;
memset(&header, 0, sizeof(header));
fd = open(fw_table[i].filename, O_RDONLY);
if (fd < 0) {
/* Keep the file along with set of unsigned PSP binaries & continue. */
fprintf(stderr, "Error opening file: %s: %s\n",
fw_table[i].filename, strerror(errno));
continue;
}
if (fstat(fd, &fd_stat)) {
/* Keep the file along with set of unsigned PSP binaries & continue. */
fprintf(stderr, "fstat error: %s\n", strerror(errno));
close(fd);
continue;
}
bytes = read_from_file_to_buf(fd, &header, sizeof(struct amd_fw_header));
if (bytes != (ssize_t)sizeof(struct amd_fw_header)) {
/* Keep the file along with set of unsigned PSP binaries & continue. */
fprintf(stderr, "%s: Error reading header from %s\n",
__func__, fw_table[i].filename);
close(fd);
continue;
}
/* If firmware header looks like invalid, assume it's not signed */
if (!header.fw_type && !header.fw_id) {
fprintf(stderr, "%s: Invalid FWID for %s\n",
__func__, fw_table[i].filename);
close(fd);
continue;
}
/* PSP binary is not signed and should not be part of signed PSP binaries
set. */
if (header.sig_opt != 1) {
close(fd);
continue;
}
buf = malloc(fd_stat.st_size);
if (!buf) {
/* Keep the file along with set of unsigned PSP binaries & continue. */
fprintf(stderr, "%s: failed to allocate memory with size %lld\n",
__func__, (long long)fd_stat.st_size);
close(fd);
continue;
}
lseek(fd, SEEK_SET, 0);
bytes = read_from_file_to_buf(fd, buf, fd_stat.st_size);
if (bytes != fd_stat.st_size) {
/* Keep the file along with set of unsigned PSP binaries & continue. */
fprintf(stderr, "%s: failed to read %s\n",
__func__, fw_table[i].filename);
free(buf);
close(fd);
continue;
}
bytes = write_from_buf_to_file(signed_rom_fd, buf, fd_stat.st_size);
if (bytes != fd_stat.st_size) {
/* Keep the file along with set of unsigned PSP binaries & continue. */
fprintf(stderr, "%s: failed to write %s\n",
__func__, fw_table[i].filename);
free(buf);
close(fd);
continue;
}
/* Write Blob alignment bytes */
align_bytes = 0;
if (fd_stat.st_size & (BLOB_ALIGNMENT - 1)) {
align_bytes = BLOB_ALIGNMENT -
(fd_stat.st_size & (BLOB_ALIGNMENT - 1));
bytes = write_from_buf_to_file(signed_rom_fd, align_data, align_bytes);
if (bytes != align_bytes) {
fprintf(stderr, "%s: failed to write alignment data for %s\n",
__func__, fw_table[i].filename);
lseek(signed_rom_fd, SEEK_CUR, -fd_stat.st_size);
free(buf);
close(fd);
continue;
}
}
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
if (add_sha(&fw_table[i], buf, fd_stat.st_size, soc_id))
exit(-1);
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
/* File is successfully processed and is part of signed PSP binaries set. */
fw_table[i].fw_id = get_psp_fw_type(soc_id, &header);
fw_table[i].addr_signed = signed_start_addr;
fw_table[i].file_size = (uint32_t)fd_stat.st_size;
signed_start_addr += fd_stat.st_size + align_bytes;
free(buf);
close(fd);
}
close(signed_rom_fd);
util/amdfwtool: Generate hashes for signed AMDFW components Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage can pass it to PSP. The PSP will use these hashes to verify the integrity of those signed firmwares. BUG=b:203597980 TEST=Build Skyrim BIOS image. Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-21 05:45:06 +01:00
/* signed_rom file name + ".hash" + '\0' */
signed_rom_hash_strlen = strlen(signed_rom) + strlen(HASH_FILE_SUFFIX) + 1;
signed_rom_hash = malloc(signed_rom_hash_strlen);
if (!signed_rom_hash) {
fprintf(stderr, "malloc(%lu) failed\n", signed_rom_hash_strlen);
exit(-1);
}
strcpy(signed_rom_hash, signed_rom);
strcat(signed_rom_hash, HASH_FILE_SUFFIX);
write_psp_firmware_hash(signed_rom_hash, fw_table);
free(signed_rom_hash);
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
}
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
static void integrate_psp_ab(context *ctx, psp_directory_table *pspdir,
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
psp_directory_table *pspdir2, ish_directory_table *ish,
amd_fw_type ab, enum platform soc_id)
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{
uint32_t count;
uint32_t current_table_save;
current_table_save = ctx->current_table;
ctx->current_table = (char *)pspdir - ctx->rom;
count = pspdir->header.num_entries;
assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
pspdir->entries[count].type = (uint8_t)ab;
pspdir->entries[count].subprog = 0;
pspdir->entries[count].rsvd = 0;
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
if (ish != NULL) {
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
ish->pl2_location = BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
ish->boot_priority = ab == AMD_FW_RECOVERYAB_A ? 0xFFFFFFFF : 1;
ish->update_retry_count = 2;
ish->glitch_retry_count = 0;
ish->psp_id = get_psp_id(soc_id);
ish->checksum = fletcher32(&ish->boot_priority,
sizeof(ish_directory_table) - sizeof(uint32_t));
pspdir->entries[count].addr =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
BUFF_TO_RUN_MODE(*ctx, ish, AMD_ADDR_REL_BIOS);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
pspdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
pspdir->entries[count].size = TABLE_ALIGNMENT;
} else {
pspdir->entries[count].addr =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
pspdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
pspdir->entries[count].size = pspdir2->header.num_entries *
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
sizeof(psp_directory_entry) +
sizeof(psp_directory_header);
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
}
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
count++;
pspdir->header.num_entries = count;
ctx->current_table = current_table_save;
}
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
static void integrate_psp_firmwares(context *ctx,
util/amdfwtool: Clarify calculations with structures Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-24 00:42:46 +01:00
psp_directory_table *pspdir,
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
psp_directory_table *pspdir2,
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
psp_directory_table *pspdir2_b,
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
amd_fw_entry *fw_table,
amdfwtool: Detect the flag multilevel to decide the actual value To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-20 08:58:22 +02:00
uint32_t cookie,
amd_cb_config *cb_config)
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
{
util/amdfwtool/amdfwtool.c: Verify it actually read bytes The function read() returns the number of bytes actually read. Program is assuming it actually read the required number of bytes without checking. This is wrong. This fixes CIDs 1353019 and 1353021 BUG=b:72062481 TEST=Build no errors Change-Id: I22d41b3de4eac5369f512f78b1b31cc1a250f787 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17 18:23:19 +01:00
ssize_t bytes;
util/amdfwtool: Fix iteration of PSP firmwares Correct an oversight in the utility that attempts to match up eligible PSP directory table entries with blob names passed on the command line. A 1:1 matchup of items shouldn't be assumed, so the i iterator shouldn't be used to walk both lists. This change has no effect on google/grunt (Family 15h Models 70h-7Fh), but eliminates blank entries of all FF's on builds of amd/bettong (F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries also affects the checksum accordingly. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 00:41:35 +01:00
unsigned int i, count;
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
int level;
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
uint32_t size;
uint64_t addr;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
uint32_t current_table_save;
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
bool recovery_ab = cb_config->recovery_ab;
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
ish_directory_table *ish_a_dir = NULL, *ish_b_dir = NULL;
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
/* This function can create a primary table, a secondary table, or a
* flattened table which contains all applicable types. These if-else
* statements infer what the caller intended. If a 2nd-level cookie
* is passed, clearly a 2nd-level table is intended. However, a
* 1st-level cookie may indicate level 1 or flattened. If the caller
* passes a pointer to a 2nd-level table, then assume not flat.
*/
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (!cb_config->multi_level)
amdfwtool: Detect the flag multilevel to decide the actual value To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-20 08:58:22 +02:00
level = PSP_BOTH;
else if (cookie == PSPL2_COOKIE)
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
level = PSP_LVL2;
else if (pspdir2)
level = PSP_LVL1;
else
level = PSP_BOTH;
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
if (recovery_ab) {
if (cookie == PSPL2_COOKIE)
level = PSP_LVL2_AB;
else if (pspdir2)
level = PSP_LVL1_AB;
else
level = PSP_BOTH_AB;
}
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
current_table_save = ctx->current_table;
ctx->current_table = (char *)pspdir - ctx->rom;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Fix iteration of PSP firmwares Correct an oversight in the utility that attempts to match up eligible PSP directory table entries with blob names passed on the command line. A 1:1 matchup of items shouldn't be assumed, so the i iterator shouldn't be used to walk both lists. This change has no effect on google/grunt (Family 15h Models 70h-7Fh), but eliminates blank entries of all FF's on builds of amd/bettong (F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries also affects the checksum accordingly. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 00:41:35 +01:00
for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) {
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
if (!(fw_table[i].level & level))
continue;
amdfwtool: Pack out-of-bounds check into a function and move Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 06:09:07 +02:00
assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
if (fw_table[i].type == AMD_TOKEN_UNLOCK) {
if (!fw_table[i].other)
continue;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
pspdir->entries[count].type = fw_table[i].type;
pspdir->entries[count].size = 4096; /* TODO: doc? */
pspdir->entries[count].addr = RUN_CURRENT(*ctx);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
pspdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
pspdir->entries[count].subprog = fw_table[i].subprog;
pspdir->entries[count].rsvd = 0;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 4096, 0x100U);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
count++;
} else if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) {
util/amdfwtool: Clarify calculations with structures Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-24 00:42:46 +01:00
pspdir->entries[count].type = fw_table[i].type;
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
pspdir->entries[count].subprog = fw_table[i].subprog;
pspdir->entries[count].rsvd = 0;
util/amdfwtool: Clarify calculations with structures Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-24 00:42:46 +01:00
pspdir->entries[count].size = 0xFFFFFFFF;
util/amdfwtool: Add argument for soft fuse override Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:16:41 +02:00
pspdir->entries[count].addr = fw_table[i].other;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
pspdir->entries[count].address_mode = 0;
util/amdfwtool: Fix iteration of PSP firmwares Correct an oversight in the utility that attempts to match up eligible PSP directory table entries with blob names passed on the command line. A 1:1 matchup of items shouldn't be assumed, so the i iterator shouldn't be used to walk both lists. This change has no effect on google/grunt (Family 15h Models 70h-7Fh), but eliminates blank entries of all FF's on builds of amd/bettong (F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries also affects the checksum accordingly. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 00:41:35 +01:00
count++;
util/amdfwtool: Align PSP NVRAM Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-11 17:44:43 +02:00
} else if (fw_table[i].type == AMD_FW_PSP_NVRAM) {
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
if (fw_table[i].filename == NULL) {
if (fw_table[i].size == 0)
continue;
size = fw_table[i].size;
addr = fw_table[i].dest;
util/amdfwtool/amdfwtool: Don't rewrite macros Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 09:58:29 +02:00
if (addr != ALIGN_UP(addr, ERASE_ALIGNMENT)) {
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
fprintf(stderr,
"Error: PSP NVRAM section not aligned with erase block size.\n\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
exit(1);
}
} else {
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
bytes = copy_blob(BUFF_CURRENT(*ctx),
fw_table[i].filename, BUFF_ROOM(*ctx));
if (bytes <= 0) {
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
exit(1);
}
util/amdfwtool/amdfwtool: Don't rewrite macros Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 09:58:29 +02:00
size = ALIGN_UP(bytes, ERASE_ALIGNMENT);
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
addr = RUN_CURRENT(*ctx);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, bytes, BLOB_ERASE_ALIGNMENT);
util/amdfwtool: Align PSP NVRAM Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-11 17:44:43 +02:00
}
pspdir->entries[count].type = fw_table[i].type;
pspdir->entries[count].subprog = fw_table[i].subprog;
pspdir->entries[count].rsvd = 0;
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
pspdir->entries[count].size = size;
pspdir->entries[count].addr = addr;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
pspdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
util/amdfwtool: Align PSP NVRAM Align the PSP's NVRAM item since it's intended to be updateable in the flash device. Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-11 17:44:43 +02:00
count++;
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
} else if (fw_table[i].filename != NULL) {
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
if (fw_table[i].addr_signed) {
pspdir->entries[count].addr =
RUN_OFFSET(*ctx, fw_table[i].addr_signed);
pspdir->entries[count].address_mode =
SET_ADDR_MODE_BY_TABLE(pspdir);
bytes = fw_table[i].file_size;
} else {
bytes = copy_blob(BUFF_CURRENT(*ctx),
fw_table[i].filename, BUFF_ROOM(*ctx));
if (bytes < 0) {
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
exit(1);
}
pspdir->entries[count].addr = RUN_CURRENT(*ctx);
pspdir->entries[count].address_mode =
SET_ADDR_MODE_BY_TABLE(pspdir);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, bytes, BLOB_ALIGNMENT);
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
}
util/amdfwtool: Add generic image copy function Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 02:40:49 +01:00
pspdir->entries[count].type = fw_table[i].type;
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
pspdir->entries[count].subprog = fw_table[i].subprog;
pspdir->entries[count].rsvd = 0;
amdfwtool: Support multiple inst entries Use the inst field when adding entries to the psp tables. Otherwise, entries that differ by the inst field will appear as duplicates with an inst of 0. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I4a84a0730976f4c65902b5c24ed13e21e95b03bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-03-07 17:00:49 +01:00
pspdir->entries[count].inst = fw_table[i].inst;
util/amdfwtool: Add generic image copy function Consolidate the code that opens, stats, copies, and closes the individual files into a single function. TEST=Verify no difference in amdfw.rom for google/grunt before and after the patch is applied Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-28 02:40:49 +01:00
pspdir->entries[count].size = (uint32_t)bytes;
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
util/amdfwtool: Fix iteration of PSP firmwares Correct an oversight in the utility that attempts to match up eligible PSP directory table entries with blob names passed on the command line. A 1:1 matchup of items shouldn't be assumed, so the i iterator shouldn't be used to walk both lists. This change has no effect on google/grunt (Family 15h Models 70h-7Fh), but eliminates blank entries of all FF's on builds of amd/bettong (F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries also affects the checksum accordingly. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-24 00:41:35 +01:00
count++;
amdfwtool: Fix some PSP2 issues 1. Change the function which integrated one firmware, to the function which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). 3. Reserve 32 more bytes in PSP2 header. It is defined by spec. It is tested, and it is true. These above changes are overlapping, hard to split them. Sorry. Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/13808 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02 07:47:27 +01:00
} else {
/* This APU doesn't have this firmware. */
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
if (recovery_ab && (pspdir2 != NULL)) {
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
if (cb_config->need_ish) { /* Need ISH */
ish_a_dir = new_ish_dir(ctx);
if (pspdir2_b != NULL)
ish_b_dir = new_ish_dir(ctx);
}
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
pspdir->header.num_entries = count;
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
AMD_FW_RECOVERYAB_A, cb_config->soc_id);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
if (pspdir2_b != NULL)
amdfwtool: Add ISH header support for A/B recovery layout Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:30:08 +02:00
integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
AMD_FW_RECOVERYAB_B, cb_config->soc_id);
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
else
util/amdfwtool: Fix ISH_B directory offset On boards which use both PSP recovery A/B layout as well as VBOOT A/B layout, ISH_B directory entry is pointing directly to PSP Level2 directory. This is not correct and either ISH_B should be marked as not present or it should point to the ISH_A directory itself which in turn point to PSP L2 directory. Fix it by choosing the latter option. BUG=None TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-02 19:34:48 +02:00
integrate_psp_ab(ctx, pspdir, pspdir2, ish_a_dir,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
AMD_FW_RECOVERYAB_B, cb_config->soc_id);
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
count = pspdir->header.num_entries;
} else if (pspdir2 != NULL) {
amdfwtool: Pack out-of-bounds check into a function and move Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 06:09:07 +02:00
assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
pspdir->entries[count].type = AMD_FW_L2_PTR;
pspdir->entries[count].subprog = 0;
pspdir->entries[count].rsvd = 0;
pspdir->entries[count].size = sizeof(pspdir2->header)
+ pspdir2->header.num_entries
* sizeof(psp_directory_entry);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
pspdir->entries[count].addr =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
BUFF_TO_RUN_MODE(*ctx, pspdir2, AMD_ADDR_REL_BIOS);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
pspdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(pspdir, AMD_ADDR_REL_BIOS);
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
count++;
}
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
fill_dir_header(pspdir, count, cookie, ctx);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
ctx->current_table = current_table_save;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
static void add_psp_firmware_entry(context *ctx,
psp_directory_table *pspdir,
void *table, amd_fw_type type, uint32_t size)
{
uint32_t count = pspdir->header.num_entries;
uint32_t index;
uint32_t current_table_save;
current_table_save = ctx->current_table;
ctx->current_table = (char *)pspdir - ctx->rom;
/* If there is an entry of "type", replace it. */
for (index = 0; index < count; index++) {
if (pspdir->entries[index].type == (uint8_t)type)
break;
}
assert_fw_entry(count, MAX_PSP_ENTRIES, ctx);
pspdir->entries[index].type = (uint8_t)type;
pspdir->entries[index].subprog = 0;
pspdir->entries[index].rsvd = 0;
pspdir->entries[index].addr = BUFF_TO_RUN(*ctx, table);
pspdir->entries[index].address_mode = SET_ADDR_MODE_BY_TABLE(pspdir);
pspdir->entries[index].size = size;
if (index == count)
count++;
pspdir->header.num_entries = count;
pspdir->header.checksum = fletcher32(&pspdir->header.num_entries,
count * sizeof(psp_directory_entry)
+ sizeof(pspdir->header.num_entries)
+ sizeof(pspdir->header.additional_info));
ctx->current_table = current_table_save;
}
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
static void *new_bios_dir(context *ctx, bool multi)
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{
void *ptr;
/*
* Force both onto boundary when multi. Primary table is after
* updatable table, so alignment ensures primary can stay intact
* if secondary is reprogrammed.
*/
if (multi)
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ERASE_ALIGNMENT);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
else
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
ptr = BUFF_CURRENT(*ctx);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
((bios_directory_hdr *) ptr)->additional_info = 0;
((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode;
ctx->current_table = ctx->current;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx,
sizeof(bios_directory_hdr) + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry),
1);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
return ptr;
}
static int locate_bdt2_bios(bios_directory_table *level2,
uint64_t *source, uint32_t *size)
{
amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-01 10:16:30 +02:00
uint32_t i;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
*source = 0;
*size = 0;
if (!level2)
return 0;
for (i = 0 ; i < level2->header.num_entries ; i++) {
if (level2->entries[i].type == AMD_BIOS_BIN) {
*source = level2->entries[i].source;
*size = level2->entries[i].size;
return 1;
}
}
return 0;
}
static int have_bios_tables(amd_bios_entry *table)
{
int i;
for (i = 0 ; table[i].type != AMD_BIOS_INVALID; i++) {
if (table[i].level & BDT_LVL1 && table[i].filename)
return 1;
}
return 0;
}
util/amdfwtool: Clarify APOB NV requirements Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-22 01:17:59 +01:00
static int find_bios_entry(amd_bios_type type)
{
int i;
for (i = 0; amd_bios_table[i].type != AMD_BIOS_INVALID; i++) {
if (amd_bios_table[i].type == type)
return i;
}
return -1;
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
static void integrate_bios_firmwares(context *ctx,
bios_directory_table *biosdir,
bios_directory_table *biosdir2,
amd_bios_entry *fw_table,
amdfwtool: Detect the flag multilevel to decide the actual value To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-20 08:58:22 +02:00
uint32_t cookie,
amd_cb_config *cb_config)
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
{
ssize_t bytes;
util/amdfwtool: Do misc cleanup - Correct command line argument for microcode patches from -u to -O - Add #if PSP_COMBO around new_combo_dir() as it's only called when that's enabled. - Remove unused variable in integrate_bios_firmwares() - Correct enum type from amd_fw_type to amd_bios_type in register_fw_addr() Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-14 04:03:34 +02:00
unsigned int i, count;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
int level;
util/amdfwtool: Clarify APOB NV requirements Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-22 01:17:59 +01:00
int apob_idx;
util/amdfwtool: Fix warning taking address of packed struct member GCC9 introduced a new warning [-Waddress-of-packed-member]. This is giving the following warning when building amdfwtool: warning: taking address of packed member of ‘struct _bios_directory_entry’ may result in an unaligned pointer value. Looking at the definition of the struct, it looks like this is probably true. Since the function being called doesn't read from the values, zeroing them out in the beginning of the function, the code just passes pointers to the temporary variables without initializing them. BUG=None TEST=Build & use AMD firmware table. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-01 18:54:11 +02:00
uint32_t size;
uint64_t source;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* This function can create a primary table, a secondary table, or a
* flattened table which contains all applicable types. These if-else
* statements infer what the caller intended. If a 2nd-level cookie
* is passed, clearly a 2nd-level table is intended. However, a
* 1st-level cookie may indicate level 1 or flattened. If the caller
* passes a pointer to a 2nd-level table, then assume not flat.
*/
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
if (!cb_config->multi_level)
amdfwtool: Detect the flag multilevel to decide the actual value To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-20 08:58:22 +02:00
level = BDT_BOTH;
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
else if (cookie == BHDL2_COOKIE)
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
level = BDT_LVL2;
else if (biosdir2)
level = BDT_LVL1;
else
level = BDT_BOTH;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
for (i = 0, count = 0; fw_table[i].type != AMD_BIOS_INVALID; i++) {
if (!(fw_table[i].level & level))
continue;
if (fw_table[i].filename == NULL && (
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
fw_table[i].type != AMD_BIOS_SIG &&
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
fw_table[i].type != AMD_BIOS_APOB &&
fw_table[i].type != AMD_BIOS_APOB_NV &&
fw_table[i].type != AMD_BIOS_L2_PTR &&
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
fw_table[i].type != AMD_BIOS_BIN &&
fw_table[i].type != AMD_BIOS_PSP_SHARED_MEM))
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
continue;
/* BIOS Directory items may have additional requirements */
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
/* SIG needs a size, else no choice but to skip */
if (fw_table[i].type == AMD_BIOS_SIG && !fw_table[i].size)
continue;
util/amdfwtool: Refactor APOB_NV requirements amdfwtool currently assumes that we MUST have an apob_nv area if we have an aopb. This is not required, so if neither the apob_nv size or base are specified, just move on. BUG=b:158363448 TEST=Build an image with no APOB_NV region. Dump regions to show that it's not there. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 00:32:25 +02:00
/* Check APOB_NV requirements */
if (fw_table[i].type == AMD_BIOS_APOB_NV) {
if (!fw_table[i].size && !fw_table[i].src)
continue; /* APOB_NV not used */
if (fw_table[i].src && !fw_table[i].size) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: APOB NV address provided, but no size\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
exit(1);
}
util/amdfwtool: Refactor APOB_NV requirements amdfwtool currently assumes that we MUST have an apob_nv area if we have an aopb. This is not required, so if neither the apob_nv size or base are specified, just move on. BUG=b:158363448 TEST=Build an image with no APOB_NV region. Dump regions to show that it's not there. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 00:32:25 +02:00
/* If the APOB isn't used, APOB_NV isn't used either */
util/amdfwtool: Clarify APOB NV requirements Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-22 01:17:59 +01:00
apob_idx = find_bios_entry(AMD_BIOS_APOB);
util/amdfwtool: Refactor APOB_NV requirements amdfwtool currently assumes that we MUST have an apob_nv area if we have an aopb. This is not required, so if neither the apob_nv size or base are specified, just move on. BUG=b:158363448 TEST=Build an image with no APOB_NV region. Dump regions to show that it's not there. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibaeacd3dcdfd73f690df61c2a19d39bbb9dcc838 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44045 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30 00:32:25 +02:00
if (apob_idx < 0 || !fw_table[apob_idx].dest)
continue; /* APOV NV not supported */
util/amdfwtool: Clarify APOB NV requirements Relocate the first size check. This was automatically continuing and not looking for the caller incorrectly passing a destination. New information indicates that the APOB_NV should always be present in the system. Augment the missing size check to inferring whether a missing size is valid, as in the case of older products, or truly missing when it's needed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51f5333de4392dec1478bd84563c053a508b9e9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-01-22 01:17:59 +01:00
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* APOB_DATA needs destination */
if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: APOB destination not provided\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
exit(1);
}
/* BIOS binary must have destination and uncompressed size. If
* no filename given, then user must provide a source address.
*/
if (fw_table[i].type == AMD_BIOS_BIN) {
if (!fw_table[i].dest || !fw_table[i].size) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
exit(1);
}
if (!fw_table[i].filename && !fw_table[i].src) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n");
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
exit(1);
}
}
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
/* PSP_SHARED_MEM needs a destination and size */
if (fw_table[i].type == AMD_BIOS_PSP_SHARED_MEM &&
(!fw_table[i].dest || !fw_table[i].size))
continue;
amdfwtool: Pack out-of-bounds check into a function and move Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 06:09:07 +02:00
assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx);
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
biosdir->entries[count].type = fw_table[i].type;
biosdir->entries[count].region_type = fw_table[i].region_type;
biosdir->entries[count].dest = fw_table[i].dest ?
fw_table[i].dest : (uint64_t)-1;
biosdir->entries[count].reset = fw_table[i].reset;
biosdir->entries[count].copy = fw_table[i].copy;
biosdir->entries[count].ro = fw_table[i].ro;
biosdir->entries[count].compressed = fw_table[i].zlib;
biosdir->entries[count].inst = fw_table[i].inst;
biosdir->entries[count].subprog = fw_table[i].subpr;
switch (fw_table[i].type) {
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
case AMD_BIOS_SIG:
/* Reserve size bytes within amdfw.rom */
biosdir->entries[count].size = fw_table[i].size;
biosdir->entries[count].source = RUN_CURRENT(*ctx);
biosdir->entries[count].address_mode =
SET_ADDR_MODE_BY_TABLE(biosdir);
memset(BUFF_CURRENT(*ctx), 0xff,
biosdir->entries[count].size);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, biosdir->entries[count].size, 0x100U);
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
break;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
case AMD_BIOS_APOB:
biosdir->entries[count].size = fw_table[i].size;
biosdir->entries[count].source = fw_table[i].src;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
break;
case AMD_BIOS_APOB_NV:
if (fw_table[i].src) {
/* If source is given, use that and its size */
biosdir->entries[count].source = fw_table[i].src;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
biosdir->entries[count].size = fw_table[i].size;
} else {
/* Else reserve size bytes within amdfw.rom */
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
biosdir->entries[count].source = RUN_CURRENT(*ctx);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
util/amdfwtool/amdfwtool: Don't rewrite macros Change-Id: Iea9dc65584c751e4d02524582b744ec9732e2c04 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14 09:58:29 +02:00
biosdir->entries[count].size = ALIGN_UP(
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
fw_table[i].size, ERASE_ALIGNMENT);
memset(BUFF_CURRENT(*ctx), 0xff,
biosdir->entries[count].size);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, biosdir->entries[count].size, 1);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
}
break;
case AMD_BIOS_BIN:
/* Don't make a 2nd copy, point to the same one */
util/amdfwtool: Fix warning taking address of packed struct member GCC9 introduced a new warning [-Waddress-of-packed-member]. This is giving the following warning when building amdfwtool: warning: taking address of packed member of ‘struct _bios_directory_entry’ may result in an unaligned pointer value. Looking at the definition of the struct, it looks like this is probably true. Since the function being called doesn't read from the values, zeroing them out in the beginning of the function, the code just passes pointers to the temporary variables without initializing them. BUG=None TEST=Build & use AMD firmware table. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-01 18:54:11 +02:00
if (level == BDT_LVL1 && locate_bdt2_bios(biosdir2, &source, &size)) {
biosdir->entries[count].source = source;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
util/amdfwtool: Fix warning taking address of packed struct member GCC9 introduced a new warning [-Waddress-of-packed-member]. This is giving the following warning when building amdfwtool: warning: taking address of packed member of ‘struct _bios_directory_entry’ may result in an unaligned pointer value. Looking at the definition of the struct, it looks like this is probably true. Since the function being called doesn't read from the values, zeroing them out in the beginning of the function, the code just passes pointers to the temporary variables without initializing them. BUG=None TEST=Build & use AMD firmware table. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-01 18:54:11 +02:00
biosdir->entries[count].size = size;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
break;
util/amdfwtool: Fix warning taking address of packed struct member GCC9 introduced a new warning [-Waddress-of-packed-member]. This is giving the following warning when building amdfwtool: warning: taking address of packed member of ‘struct _bios_directory_entry’ may result in an unaligned pointer value. Looking at the definition of the struct, it looks like this is probably true. Since the function being called doesn't read from the values, zeroing them out in the beginning of the function, the code just passes pointers to the temporary variables without initializing them. BUG=None TEST=Build & use AMD firmware table. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2f1e0aede8563e39ab0f2ec6daed91d6431eac43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-01 18:54:11 +02:00
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* level 2, or level 1 and no copy found in level 2 */
biosdir->entries[count].source = fw_table[i].src;
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
biosdir->entries[count].dest = fw_table[i].dest;
biosdir->entries[count].size = fw_table[i].size;
if (!fw_table[i].filename)
break;
bytes = copy_blob(BUFF_CURRENT(*ctx),
fw_table[i].filename, BUFF_ROOM(*ctx));
if (bytes <= 0) {
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
exit(1);
}
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].source =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
RUN_CURRENT_MODE(*ctx, AMD_ADDR_REL_BIOS);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, bytes, 0x100U);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
break;
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
case AMD_BIOS_PSP_SHARED_MEM:
biosdir->entries[count].dest = fw_table[i].dest;
biosdir->entries[count].size = fw_table[i].size;
break;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
default: /* everything else is copied from input */
if (fw_table[i].type == AMD_BIOS_APCB ||
fw_table[i].type == AMD_BIOS_APCB_BK)
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, 0, ERASE_ALIGNMENT);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
bytes = copy_blob(BUFF_CURRENT(*ctx),
fw_table[i].filename, BUFF_ROOM(*ctx));
if (bytes <= 0) {
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
exit(1);
}
biosdir->entries[count].size = (uint32_t)bytes;
biosdir->entries[count].source = RUN_CURRENT(*ctx);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode = SET_ADDR_MODE_BY_TABLE(biosdir);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(ctx, bytes, 0x100U);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
break;
}
count++;
}
if (biosdir2) {
amdfwtool: Pack out-of-bounds check into a function and move Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-30 06:09:07 +02:00
assert_fw_entry(count, MAX_BIOS_ENTRIES, ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
biosdir->entries[count].type = AMD_BIOS_L2_PTR;
amdfwtool: Set the region_type as 0 for entry "BIOS level 2" This region_type is actually not used. But we need to set it explicitly as a known value. We can refer "PSP spec #55758" or the link below: https://doc.coreboot.org/soc/amd/psp_integration.html Change-Id: I8b914f9f02beecce707aba86248826cd9208e6c0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-24 10:11:12 +02:00
biosdir->entries[count].region_type = 0;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
biosdir->entries[count].size =
+ MAX_BIOS_ENTRIES
* sizeof(bios_directory_entry);
biosdir->entries[count].source =
BUFF_TO_RUN(*ctx, biosdir2);
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
biosdir->entries[count].address_mode =
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
SET_ADDR_MODE(biosdir, AMD_ADDR_REL_BIOS);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
biosdir->entries[count].subprog = 0;
biosdir->entries[count].inst = 0;
biosdir->entries[count].copy = 0;
biosdir->entries[count].compressed = 0;
biosdir->entries[count].dest = -1;
biosdir->entries[count].reset = 0;
biosdir->entries[count].ro = 0;
count++;
}
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
fill_dir_header(biosdir, count, cookie, ctx);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
}
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
enum {
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
AMDFW_OPT_CONFIG = 'c',
AMDFW_OPT_DEBUG = 'd',
AMDFW_OPT_HELP = 'h',
AMDFW_OPT_LIST_DEPEND = 'l',
AMDFW_OPT_XHCI = 128,
AMDFW_OPT_IMC,
AMDFW_OPT_GEC,
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
AMDFW_OPT_RECOVERY_AB,
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
AMDFW_OPT_RECOVERY_AB_SINGLE_COPY,
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
AMDFW_OPT_USE_COMBO,
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
AMDFW_OPT_MULTILEVEL,
AMDFW_OPT_NVRAM,
AMDFW_OPT_FUSE,
AMDFW_OPT_UNLOCK,
AMDFW_OPT_WHITELIST,
AMDFW_OPT_USE_PSPSECUREOS,
AMDFW_OPT_LOAD_MP2FW,
AMDFW_OPT_LOAD_S0I3,
amdfwtool: Add options to support mainboard specific SPL table For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 04:51:26 +01:00
AMDFW_OPT_SPL_TABLE,
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
AMDFW_OPT_VERSTAGE,
AMDFW_OPT_VERSTAGE_SIG,
AMDFW_OPT_INSTANCE,
AMDFW_OPT_APCB,
AMDFW_OPT_APOBBASE,
AMDFW_OPT_BIOSBIN,
AMDFW_OPT_BIOSBIN_SOURCE,
AMDFW_OPT_BIOSBIN_DEST,
AMDFW_OPT_BIOS_UNCOMP_SIZE,
util/amdfwtool: Add option to indicate uncompressed BIOS binary amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS directory entry) is always compressed. On boards using vboot, sometimes PSP BIOS binary is uncompressed - specifically when CBFS verification is enabled and verified boot starts in bootblock. Add an option to indicate PSP BIOS binary is uncompressed. BUG=b:261792282 TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled. Boot to OS. Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-22 23:45:56 +01:00
AMDFW_OPT_BIOSBIN_UNCOMP,
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
AMDFW_OPT_UCODE,
AMDFW_OPT_APOB_NVBASE,
AMDFW_OPT_APOB_NVSIZE,
AMDFW_OPT_OUTPUT,
AMDFW_OPT_FLASHSIZE,
AMDFW_OPT_LOCATION,
AMDFW_OPT_ANYWHERE,
AMDFW_OPT_SHAREDMEM,
AMDFW_OPT_SHAREDMEM_SIZE,
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
AMDFW_OPT_SIGNED_OUTPUT,
AMDFW_OPT_SIGNED_ADDR,
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
AMDFW_OPT_BODY_LOCATION,
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
/* begin after ASCII characters */
LONGOPT_SPI_READ_MODE = 256,
LONGOPT_SPI_SPEED = 257,
LONGOPT_SPI_MICRON_FLAG = 258,
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
LONGOPT_BIOS_SIG = 259,
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
LONGOPT_NVRAM_BASE = 260,
LONGOPT_NVRAM_SIZE = 261,
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
};
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
static char const optstring[] = {AMDFW_OPT_CONFIG, ':',
AMDFW_OPT_DEBUG, AMDFW_OPT_HELP, AMDFW_OPT_LIST_DEPEND
};
util/amdfwtool: Add PSP2 options to optstring Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> (cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de) Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/17147 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Zheng Bao <fishbaozi@gmail.com>
2016-09-21 05:05:45 +02:00
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
static struct option long_options[] = {
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"xhci", required_argument, 0, AMDFW_OPT_XHCI },
{"imc", required_argument, 0, AMDFW_OPT_IMC },
{"gec", required_argument, 0, AMDFW_OPT_GEC },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* PSP Directory Table items */
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
{"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB },
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
{"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY },
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
{"use-combo", no_argument, 0, AMDFW_OPT_USE_COMBO },
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL },
{"nvram", required_argument, 0, AMDFW_OPT_NVRAM },
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
{"nvram-base", required_argument, 0, LONGOPT_NVRAM_BASE },
{"nvram-size", required_argument, 0, LONGOPT_NVRAM_SIZE },
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE },
{"token-unlock", no_argument, 0, AMDFW_OPT_UNLOCK },
{"whitelist", required_argument, 0, AMDFW_OPT_WHITELIST },
{"use-pspsecureos", no_argument, 0, AMDFW_OPT_USE_PSPSECUREOS },
{"load-mp2-fw", no_argument, 0, AMDFW_OPT_LOAD_MP2FW },
{"load-s0i3", no_argument, 0, AMDFW_OPT_LOAD_S0I3 },
amdfwtool: Add options to support mainboard specific SPL table For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 04:51:26 +01:00
{"spl-table", required_argument, 0, AMDFW_OPT_SPL_TABLE },
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"verstage", required_argument, 0, AMDFW_OPT_VERSTAGE },
{"verstage_sig", required_argument, 0, AMDFW_OPT_VERSTAGE_SIG },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* BIOS Directory Table items */
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"instance", required_argument, 0, AMDFW_OPT_INSTANCE },
{"apcb", required_argument, 0, AMDFW_OPT_APCB },
{"apob-base", required_argument, 0, AMDFW_OPT_APOBBASE },
{"bios-bin", required_argument, 0, AMDFW_OPT_BIOSBIN },
{"bios-bin-src", required_argument, 0, AMDFW_OPT_BIOSBIN_SOURCE },
{"bios-bin-dest", required_argument, 0, AMDFW_OPT_BIOSBIN_DEST },
{"bios-uncomp-size", required_argument, 0, AMDFW_OPT_BIOS_UNCOMP_SIZE },
util/amdfwtool: Add option to indicate uncompressed BIOS binary amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS directory entry) is always compressed. On boards using vboot, sometimes PSP BIOS binary is uncompressed - specifically when CBFS verification is enabled and verified boot starts in bootblock. Add an option to indicate PSP BIOS binary is uncompressed. BUG=b:261792282 TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled. Boot to OS. Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-22 23:45:56 +01:00
{"bios-bin-uncomp", no_argument, 0, AMDFW_OPT_BIOSBIN_UNCOMP },
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
{"bios-sig-size", required_argument, 0, LONGOPT_BIOS_SIG },
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"ucode", required_argument, 0, AMDFW_OPT_UCODE },
{"apob-nv-base", required_argument, 0, AMDFW_OPT_APOB_NVBASE },
{"apob-nv-size", required_argument, 0, AMDFW_OPT_APOB_NVSIZE },
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
/* Embedded Firmware Structure items*/
{"spi-read-mode", required_argument, 0, LONGOPT_SPI_READ_MODE },
{"spi-speed", required_argument, 0, LONGOPT_SPI_SPEED },
{"spi-micron-flag", required_argument, 0, LONGOPT_SPI_MICRON_FLAG },
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
{"body-location", required_argument, 0, AMDFW_OPT_BODY_LOCATION },
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* other */
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"output", required_argument, 0, AMDFW_OPT_OUTPUT },
{"flashsize", required_argument, 0, AMDFW_OPT_FLASHSIZE },
{"location", required_argument, 0, AMDFW_OPT_LOCATION },
{"anywhere", no_argument, 0, AMDFW_OPT_ANYWHERE },
{"sharedmem", required_argument, 0, AMDFW_OPT_SHAREDMEM },
{"sharedmem-size", required_argument, 0, AMDFW_OPT_SHAREDMEM_SIZE },
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
{"signed-output", required_argument, 0, AMDFW_OPT_SIGNED_OUTPUT },
{"signed-addr", required_argument, 0, AMDFW_OPT_SIGNED_ADDR },
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
{"config", required_argument, 0, AMDFW_OPT_CONFIG },
{"debug", no_argument, 0, AMDFW_OPT_DEBUG },
{"help", no_argument, 0, AMDFW_OPT_HELP },
{"list", no_argument, 0, AMDFW_OPT_LIST_DEPEND },
util/amdfwtool: Add fanless SMU firmware options The Stoney Ridge program has OPNs that are considered fanless. These APUs are strapped to search for unique SMU firmware, indicated by Type[8]=1 in the directory table entry. Add new options to amdfwtool and include the blobs in the build with the appropriate bit set in the Type encoding. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-by: Marc Jones <marcj303@gmail.com> (cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da) Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18991 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-17 23:30:51 +01:00
{NULL, 0, 0, 0 }
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
};
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
void register_fw_fuse(char *str)
util/amdfwtool: Add argument for soft fuse override Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:16:41 +02:00
{
amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-01 10:16:30 +02:00
uint32_t i;
util/amdfwtool: Add argument for soft fuse override Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:16:41 +02:00
for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN)
continue;
amd_psp_fw_table[i].other = strtoull(str, NULL, 16);
return;
}
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
static void register_fw_token_unlock(void)
{
amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-01 10:16:30 +02:00
uint32_t i;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK)
continue;
amd_psp_fw_table[i].other = 1;
return;
}
}
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[])
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
{
util/amdfwtool: fix clang warnings Various fixes for clang warnings: warning: arithmetic on a pointer to void is a GNU extension - change *rom from void* to char* and cast back to void* as needed warning: implicit conversion changes signedness - In ALIGN macro, pass in value as unsigned warning: no previous prototype for function - Change functions to static warning: no previous extern declaration for non-static variable - Change global variables to static warning: comparison of integers of different signs - Make loop variable 'i' unsigned warning: variable 'output' may be uninitialized - Make sure an output filename was specified warning: implicit conversion loses integer precision - cast fd_stat.st_size to the appropriate type Change-Id: I0134a79c00938e121e63b52fd63bd502f4cb9e99 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17322 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 18:44:18 +01:00
unsigned int i;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Fix whitespace Change-Id: I33e41b745e7ec55ed39d7125fc74b1619d28bb54 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17325 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-08 19:34:02 +01:00
for (i = 0; i < sizeof(amd_fw_table) / sizeof(amd_fw_entry); i++) {
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
if (amd_fw_table[i].type == type) {
amd_fw_table[i].filename = filename;
return;
}
}
util/amdfwtool: Remove duplicate PSP2 support There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:50:37 +01:00
for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
if (amd_psp_fw_table[i].type != type)
continue;
if (amd_psp_fw_table[i].subprog == sub) {
util/amdfwtool: Remove duplicate PSP2 support There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:50:37 +01:00
amd_psp_fw_table[i].filename = filename;
return;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}
}
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[])
{
amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-01 10:16:30 +02:00
uint32_t i;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
if (amd_bios_table[i].type == type
&& amd_bios_table[i].inst == ins
&& amd_bios_table[i].subpr == sub) {
amd_bios_table[i].filename = name;
return;
}
}
}
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
static void register_amd_psp_fw_addr(amd_fw_type type, int sub,
char *dst_str, char *size_str)
{
unsigned int i;
for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) {
if (amd_psp_fw_table[i].type != type)
continue;
if (amd_psp_fw_table[i].subprog == sub) {
if (dst_str)
amd_psp_fw_table[i].dest = strtoull(dst_str, NULL, 16);
if (size_str)
amd_psp_fw_table[i].size = strtoul(size_str, NULL, 16);
return;
}
}
}
static void register_bios_fw_addr(amd_bios_type type, char *src_str,
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
char *dst_str, char *size_str)
{
amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-01 10:16:30 +02:00
uint32_t i;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) {
if (amd_bios_table[i].type != type)
continue;
if (src_str)
amd_bios_table[i].src = strtoull(src_str, NULL, 16);
if (dst_str)
amd_bios_table[i].dest = strtoull(dst_str, NULL, 16);
if (size_str)
amd_bios_table[i].size = strtoul(size_str, NULL, 16);
return;
}
}
amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:53:51 +02:00
static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config,
embedded_firmware *amd_romsig, uint8_t efs_spi_readmode,
uint8_t efs_spi_speed, uint8_t efs_spi_micron_flag)
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
{
if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n");
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
return 1;
}
amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:53:51 +02:00
/* amd_romsig->efs_gen introduced after RAVEN/PICASSO.
* Leave as 0xffffffff for first gen */
if (cb_config->second_gen) {
amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
amd_romsig->efs_gen.reserved = 0;
} else {
amdfwtool: Add a macro to set explicitly second gen for old SOCs It is more reasonable than getting the value from memset. For the reserved bits, keep them as they were for old SOCs. Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:50:07 +02:00
amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
amd_romsig->efs_gen.reserved = ~0;
amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:53:51 +02:00
}
switch (soc_id) {
amdfwtool: Add SOC family definition for Carrizo For Carrizo, the soc name was set as UNKNOWN. The change is supposed to be binary unmodified, except the SPI settings. According to the spec, the Stoneyridge and Carrizo have the same definition of SPI setting in EFS. Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-17 05:52:30 +02:00
case PLATFORM_CARRIZO:
amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:53:51 +02:00
case PLATFORM_STONEYRIDGE:
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode;
amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed;
break;
case PLATFORM_RAVEN:
case PLATFORM_PICASSO:
amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode;
amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed;
switch (efs_spi_micron_flag) {
case 0:
amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xff;
break;
case 1:
amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa;
break;
default:
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n");
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
return 1;
}
break;
case PLATFORM_RENOIR:
case PLATFORM_LUCIENNE:
amdfwtool: Add support of cezanne and renoir Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 16:00:48 +01:00
case PLATFORM_CEZANNE:
amdfwtool: Add new SOC mendocino Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-12 10:30:19 +02:00
case PLATFORM_MENDOCINO:
amdfwtool: Add missing code for checking new family phoenix & glinda Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-16 14:32:43 +02:00
case PLATFORM_PHOENIX:
case PLATFORM_GLINDA:
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode;
amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed;
switch (efs_spi_micron_flag) {
case 0:
amd_romsig->micron_detect_f17_mod_30_3f = 0xff;
break;
case 1:
amd_romsig->micron_detect_f17_mod_30_3f = 0xaa;
break;
case 2:
amd_romsig->micron_detect_f17_mod_30_3f = 0x55;
break;
default:
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n");
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
return 1;
}
break;
case PLATFORM_UNKNOWN:
default:
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: Invalid SOC name.\n\n");
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
return 1;
}
return 0;
}
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
static ssize_t write_body(char *output, void *body_offset, ssize_t body_size, context *ctx)
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
{
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
char body_name[PATH_MAX], body_tmp_name[PATH_MAX];
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
int ret;
int fd;
ssize_t bytes = -1;
/* Create a tmp file and rename it at the end so that make does not get confused
if amdfwtool is killed for some unexpected reasons. */
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
ret = snprintf(body_tmp_name, sizeof(body_tmp_name), "%s%s%s",
output, BODY_FILE_SUFFIX, TMP_FILE_SUFFIX);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
if (ret < 0) {
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
fprintf(stderr, "Error %s forming BODY tmp file name: %d\n",
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
strerror(errno), ret);
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
exit(1);
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
} else if ((unsigned int)ret >= sizeof(body_tmp_name)) {
fprintf(stderr, "BODY File name %d > %zu\n", ret, sizeof(body_tmp_name));
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
exit(1);
}
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
fd = open(body_tmp_name, O_RDWR | O_CREAT | O_TRUNC, 0666);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
if (fd < 0) {
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
fprintf(stderr, "Error: Opening %s file: %s\n", body_tmp_name, strerror(errno));
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
exit(1);
}
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
bytes = write_from_buf_to_file(fd, body_offset, body_size);
if (bytes != body_size) {
fprintf(stderr, "Error: Writing to file %s failed\n", body_tmp_name);
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
exit(1);
}
close(fd);
/* Rename the tmp file */
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
ret = snprintf(body_name, sizeof(body_name), "%s%s", output, BODY_FILE_SUFFIX);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
if (ret < 0) {
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
fprintf(stderr, "Error %s forming BODY file name: %d\n", strerror(errno), ret);
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
exit(1);
}
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
if (rename(body_tmp_name, body_name)) {
fprintf(stderr, "Error: renaming file %s to %s\n", body_tmp_name, body_name);
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(ctx);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
exit(1);
}
return bytes;
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
int main(int argc, char **argv)
{
util/amdfwtool: Remove duplicate PSP2 support There are effectively two unique sets of arguments for the utility, causing one of two tables to be constructed. Both tables are identical, however, and therefore the only practical difference is the offset in the Embedded Firmware Structure which holds the pointer to the table. This patch is part 2 of 2 to reduce the number of command-line options to amdfwtool. Part 1 added the --combo-capable option that helps put the PSP directory pointer in the correct location. Part 2 removes the duplicated table, the support code, options, and updates the usage text. TEST=Build before/after images for grunt, bettong, apu2, and diff hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO defined as 1. BUG=b:126691068 Change-Id: I542a7f5023137f30fbe00533452d4448117df487 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:50:37 +01:00
int c;
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
int retval = 0;
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
char *tmp;
util/amdfwtool: Clarify calculations with structures Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-24 00:42:46 +01:00
embedded_firmware *amd_romsig;
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
psp_directory_table *pspdir = NULL;
psp_directory_table *pspdir2 = NULL;
psp_directory_table *pspdir2_b = NULL;
amdfwtool: combo: Add combo feature for BIOS table It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-18 09:54:47 +02:00
psp_combo_directory *psp_combo_dir = NULL, *bhd_combo_dir = NULL;
util/amdfwtool: Add argument for soft fuse override Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:16:41 +02:00
int fuse_defined = 0;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
int targetfd;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
char *output = NULL, *config = NULL;
FILE *config_handle;
amdfwtool: Remove the assumption of ROM_SIZE Every platform passes (and need to) the --flashsize to the command parameter, so we remove the macro definition about a built-time romsize defined in Makefile. Change-Id: I894e833ed23a7da38b36986b624e7dcdf1f4090c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-28 04:36:29 +02:00
context ctx = { 0 };
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* Values cleared after each firmware or parameter, regardless if N/A */
uint8_t sub = 0, instance = 0;
amdfwtool: Change the variable name to body_location The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-02 03:55:56 +01:00
uint32_t body_location = 0;
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
uint32_t efs_location = 0;
util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-07 22:16:39 +02:00
bool any_location = 0;
util/amdfwtool: Add option for directory location The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 22:16:04 +02:00
uint32_t romsig_offset;
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
uint32_t rom_base_address;
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
uint8_t efs_spi_readmode = 0xff;
uint8_t efs_spi_speed = 0xff;
uint8_t efs_spi_micron_flag = 0xff;
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
const char *signed_output_file = NULL;
uint64_t signed_start_addr = 0x0;
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
util/amdfwtool: Initalize all variables before use Not all of the fields of the amd_cb_config structure were properly initialized. Rather than initialize each field individually, initialize the entire structure to 0. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-06-29 19:54:57 +02:00
amd_cb_config cb_config = { 0 };
amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:39:13 +01:00
int debug = 0;
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
int list_deps = 0;
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
ctx.current_pointer_saved = 0xFFFFFFFF;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
while (1) {
int optindex = 0;
util/amdfwtool: Add option to indicate uncompressed BIOS binary amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS directory entry) is always compressed. On boards using vboot, sometimes PSP BIOS binary is uncompressed - specifically when CBFS verification is enabled and verified boot starts in bootblock. Add an option to indicate PSP BIOS binary is uncompressed. BUG=b:261792282 TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled. Boot to OS. Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-22 23:45:56 +01:00
int bios_tbl_index = -1;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
c = getopt_long(argc, argv, optstring, long_options, &optindex);
if (c == -1)
break;
switch (c) {
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_XHCI:
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
register_fw_filename(AMD_FW_XHCI, sub, optarg);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_IMC:
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
register_fw_filename(AMD_FW_IMC, sub, optarg);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_GEC:
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
register_fw_filename(AMD_FW_GEC, sub, optarg);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
break;
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
case AMDFW_OPT_RECOVERY_AB:
cb_config.recovery_ab = true;
break;
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY:
cb_config.recovery_ab = true;
cb_config.recovery_ab_single_copy = true;
break;
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
case AMDFW_OPT_USE_COMBO:
cb_config.use_combo = true;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_MULTILEVEL:
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
cb_config.multi_level = true;
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_UNLOCK:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
register_fw_token_unlock();
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
cb_config.unlock_secure = true;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_USE_PSPSECUREOS:
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
cb_config.use_secureos = true;
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_INSTANCE:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
instance = strtoul(optarg, &tmp, 16);
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_LOAD_MP2FW:
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
cb_config.load_mp2_fw = true;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_NVRAM:
util/amdfwtool: Split type field for PSP entries Separate the type field for the PSP directory table to better match the AMD Platform Security Processor BIOS Architecture Guide (order #55758, NDA only). Instead of a 32-bit type, change to an 8-bit value and an 8-bit subprogram field to allow for a more generic application across family/model products. This patch also eliminates the "fanless" types, previously added for stoneyridge, and converts the --smufnfirmware and --smufnfirmware2 arguments to use a subprogram value of 1. Subsequent patches will change the stoneyridge makefile to use the new option, and eliminate the fanless arguments. TEST=Boot google/grunt, confirm no difference in amdfw.rom file. BUG=b:126691068 Change-Id: If8f33000c31cba21f286f54459de185c21e46268 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04 18:31:03 +01:00
register_fw_filename(AMD_FW_PSP_NVRAM, sub, optarg);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_FUSE:
util/amdfwtool: Add argument for soft fuse override Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:16:41 +02:00
register_fw_fuse(optarg);
fuse_defined = 1;
sub = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_APCB:
amdfwtool: Register APCB and APCB_BK respectively We took the assumption the APCB(0x60) and APCB_BK(0x68) are the same file. For picasso, they are. For later programe, they are not. Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04 09:39:38 +01:00
if ((instance & 0xF0) == 0)
register_bdt_data(AMD_BIOS_APCB, sub, instance & 0xF, optarg);
else
register_bdt_data(AMD_BIOS_APCB_BK, sub,
instance & 0xF, optarg);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_APOBBASE:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* APOB destination */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_APOB, 0, optarg, 0);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_APOB_NVBASE:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* APOB NV source */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_APOB_NV, optarg, 0, 0);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_APOB_NVSIZE:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* APOB NV size */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_APOB_NV, 0, 0, optarg);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_BIOSBIN:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
register_bdt_data(AMD_BIOS_BIN, sub, instance, optarg);
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_BIOSBIN_SOURCE:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* BIOS source */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_BIN, optarg, 0, 0);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_BIOSBIN_DEST:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* BIOS destination */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_BIN, 0, optarg, 0);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_BIOS_UNCOMP_SIZE:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* BIOS destination size */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_BIN, 0, 0, optarg);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
sub = instance = 0;
break;
util/amdfwtool: Add option to indicate uncompressed BIOS binary amdfwtool always assumes that the PSP BIOS binary (type 0x62 BIOS directory entry) is always compressed. On boards using vboot, sometimes PSP BIOS binary is uncompressed - specifically when CBFS verification is enabled and verified boot starts in bootblock. Add an option to indicate PSP BIOS binary is uncompressed. BUG=b:261792282 TEST=Build Skyrim BIOS with x86 verstage and CBFS Verification enabled. Boot to OS. Change-Id: I4d56c0ba451b194043ebb5cdb0f2b27482beef1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-12-22 23:45:56 +01:00
case AMDFW_OPT_BIOSBIN_UNCOMP:
bios_tbl_index = find_bios_entry(AMD_BIOS_BIN);
if (bios_tbl_index != -1)
amd_bios_table[bios_tbl_index].zlib = 0;
break;
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
case LONGOPT_BIOS_SIG:
/* BIOS signature size */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_SIG, 0, 0, optarg);
util/amdfwtool: Add changes to reserve BIOS SIG changes to reserve space for AMD_BIOS_SIG when BIOS image is signed with RTMSignature. Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-07-29 07:36:40 +02:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_UCODE:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
register_bdt_data(AMD_BIOS_UCODE, sub,
instance, optarg);
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_LOAD_S0I3:
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
cb_config.s0i3 = true;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
break;
amdfwtool: Add options to support mainboard specific SPL table For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 04:51:26 +01:00
case AMDFW_OPT_SPL_TABLE:
register_fw_filename(AMD_FW_SPL, sub, optarg);
sub = instance = 0;
cb_config.have_mb_spl = true;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_WHITELIST:
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
register_fw_filename(AMD_FW_PSP_WHITELIST, sub, optarg);
sub = instance = 0;
amdfwtool: Change the flag value to type bool Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 11:56:47 +01:00
cb_config.have_whitelist = true;
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_VERSTAGE:
util/amdfwtool: Add option to build verstage binary into the PSP For AMD's Family17h processors, verstage needs to be run in the PSP, before memory is initialized. This adds that binary into the PSP directory. See the Family17h documentation in the coreboot documentation directory for more information. BUG=b:137338769 TEST=Build, add test binary to mandolin board, boot Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-14 04:13:07 +02:00
register_fw_filename(AMD_FW_PSP_VERSTAGE, sub, optarg);
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_VERSTAGE_SIG:
util/amdfwtool: Add PSP verstage signature entry Add the field for the PSP verstage signature entry. This adds the public key signing token to the PSP Directory table to verify the signed PSP verstage binary BUG=b:166100797 TEST=Build in a file and verify that it's present with the correct ID. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7525045d8746b6857979d07b02758ab4d4835026 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Eric Peers <epeers@google.com>
2020-09-01 17:36:59 +02:00
register_fw_filename(AMD_FW_VERSTAGE_SIG, sub, optarg);
sub = instance = 0;
break;
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
case AMDFW_OPT_SIGNED_OUTPUT:
signed_output_file = optarg;
sub = instance = 0;
break;
case AMDFW_OPT_SIGNED_ADDR:
signed_start_addr = strtoull(optarg, NULL, 10);
sub = instance = 0;
break;
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
case LONGOPT_SPI_READ_MODE:
efs_spi_readmode = strtoull(optarg, NULL, 16);
sub = instance = 0;
break;
case LONGOPT_SPI_SPEED:
efs_spi_speed = strtoull(optarg, NULL, 16);
sub = instance = 0;
break;
case LONGOPT_SPI_MICRON_FLAG:
efs_spi_micron_flag = strtoull(optarg, NULL, 16);
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_OUTPUT:
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
output = optarg;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_FLASHSIZE:
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16);
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
if (*tmp != '\0') {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: ROM size specified"
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
" incorrectly (%s)\n\n", optarg);
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
retval = 1;
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
}
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_LOCATION:
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
efs_location = (uint32_t)strtoul(optarg, &tmp, 16);
util/amdfwtool: Add option for directory location The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 22:16:04 +02:00
if (*tmp != '\0') {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: Directory Location specified"
util/amdfwtool: Add option for directory location The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 22:16:04 +02:00
" incorrectly (%s)\n\n", optarg);
retval = 1;
}
amdfwtool: Change the variable name to body_location The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-02 03:55:56 +01:00
if (body_location == 0)
body_location = efs_location;
util/amdfwtool: Add option for directory location The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 22:16:04 +02:00
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_ANYWHERE:
util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-07 22:16:39 +02:00
any_location = 1;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_SHAREDMEM:
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
/* shared memory destination */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, 0, optarg, 0);
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_SHAREDMEM_SIZE:
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
/* shared memory size */
util/amdfwtool: Add support for PSP NVRAM base addr and size Add parameters to support adding the location and size of the PSP NVRAM area to the PSP directory table. Verified this change on PCO based Bilby platform. Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-28 21:21:08 +02:00
register_bios_fw_addr(AMD_BIOS_PSP_SHARED_MEM, NULL, NULL, optarg);
sub = instance = 0;
break;
case LONGOPT_NVRAM_BASE:
/* PSP NV base */
register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, optarg, 0);
sub = instance = 0;
break;
case LONGOPT_NVRAM_SIZE:
/* PSP NV size */
register_amd_psp_fw_addr(AMD_FW_PSP_NVRAM, sub, 0, optarg);
util/amdfwtool: Add option for setting PSP/FW shared memory location This tells the PSP where in main memory to copy the vboot workbuf. BUG=b:152576063 TEST=Build sharedmem destination into AMDFW, verify shared memory gets placed at that location. Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519 Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 22:59:36 +02:00
sub = instance = 0;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_CONFIG:
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
config = optarg;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_DEBUG:
amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:39:13 +01:00
debug = 1;
break;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_HELP:
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
usage();
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
return 0;
amdfwtool: Remove the misleading option characters Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-04-27 11:21:54 +02:00
case AMDFW_OPT_LIST_DEPEND:
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
list_deps = 1;
break;
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
case AMDFW_OPT_BODY_LOCATION:
amdfwtool: Change the variable name to body_location The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-02 03:55:56 +01:00
body_location = (uint32_t)strtoul(optarg, &tmp, 16);
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
if (*tmp != '\0') {
fprintf(stderr, "Error: Body Location specified"
" incorrectly (%s)\n\n", optarg);
retval = 1;
}
break;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
default:
break;
}
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
if (config) {
config_handle = fopen(config, "r");
if (config_handle == NULL) {
fprintf(stderr, "Can not open file %s for reading: %s\n",
config, strerror(errno));
exit(1);
}
if (process_config(config_handle, &cb_config, list_deps) == 0) {
fprintf(stderr, "Configuration file %s parsing error\n", config);
fclose(config_handle);
exit(1);
}
fclose(config_handle);
}
amdfwtool: Add an option to show debug message Change-Id: I3e3bcc2c9e1b3edfed1ce845c1603b2a9a2bb044 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:39:13 +01:00
/* For debug. */
if (debug) {
dump_psp_firmwares(amd_psp_fw_table);
dump_bdt_firmwares(amd_bios_table);
}
util/amdfwtool: Add argument for soft fuse override Allow the soc build to pass a soft fuse value to the utility. This helps maintain compatibility across PSP generations. Add a generic 'other' item to the amd_fw_entry structure that may be used by non-fuse entries in the future. TEST=Verify google/grunt amdfw.rom unchanged before and after. Compare internal board using override before and after. Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-01 18:16:41 +02:00
if (!fuse_defined)
register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN);
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
if (!output && !list_deps) {
fprintf(stderr, "Error: Output value is not specified.\n\n");
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
retval = 1;
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
if ((ctx.rom_size % 1024 != 0) && !list_deps) {
fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of"
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
" 1024 bytes.\n\n", ctx.rom_size);
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
retval = 1;
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
if ((ctx.rom_size < MIN_ROM_KB * 1024) && !list_deps) {
fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n",
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
ctx.rom_size / 1024, MIN_ROM_KB);
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
retval = 1;
}
if (retval) {
usage();
return retval;
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
}
amdfwtool: Take a config file instead of command line parameters To verify the consistency, see if timeless builds with and without this patch result in identical coreboot.rom files. BUG=b:154032833 TEST=Build & boot on mandolin Change-Id: Icae73d0730106aab687486e555ba947796e5e757 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-28 04:38:09 +01:00
if (list_deps) {
return retval;
}
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
printf(" AMDFWTOOL Using ROM size of %dKB\n", ctx.rom_size / 1024);
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1;
amdfwtool: Check the validation of EFS & body relative address We need to considering the case the EFS header is given as a relative address and the other, body location, is given as an absolute one. So we convert both of them to relative and check the validation. For relative address case, the location should be between 0 and data size. Change-Id: I7898bfbca02f5eb1c0fb7c456dc1935bddf685b1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-14 06:23:35 +01:00
if (efs_location & 0xFF000000)
efs_location = efs_location - rom_base_address;
if (body_location & 0xFF000000)
body_location = body_location - rom_base_address;
if (efs_location && efs_location > ctx.rom_size) {
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
fprintf(stderr, "Error: EFS/Directory location outside of ROM.\n\n");
return 1;
}
amdfwtool: Check the validation of EFS & body relative address We need to considering the case the EFS header is given as a relative address and the other, body location, is given as an absolute one. So we convert both of them to relative and check the validation. For relative address case, the location should be between 0 and data size. Change-Id: I7898bfbca02f5eb1c0fb7c456dc1935bddf685b1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-14 06:23:35 +01:00
if (body_location && body_location > ctx.rom_size) {
fprintf(stderr, "Error: Body location outside of ROM.\n\n");
return 1;
}
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
amdfwtool: Change the variable name to body_location The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-02 03:55:56 +01:00
if (!efs_location && body_location) {
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
fprintf(stderr, "Error AMDFW body location specified without EFS location.\n");
return 1;
}
amdfwtool: Change the variable name to body_location The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-02 03:55:56 +01:00
if (body_location != efs_location &&
body_location < ALIGN(efs_location + sizeof(embedded_firmware), BLOB_ALIGNMENT)) {
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
fprintf(stderr, "Error: Insufficient space between EFS and Blobs.\n");
fprintf(stderr, " Require safe spacing of 256 bytes\n");
util/amdfwtool: Add option for directory location The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 22:16:04 +02:00
return 1;
}
util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-07 22:16:39 +02:00
if (any_location) {
amdfwtool: Change the variable name to body_location The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-02 03:55:56 +01:00
if ((body_location & 0x3f) || (efs_location & 0x3f)) {
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
fprintf(stderr, "Error: Invalid Directory/EFS location.\n");
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, " Valid locations are 64-byte aligned\n");
util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-07 22:16:39 +02:00
return 1;
}
} else {
amdfwtool: Allow the location to be a relative address When the BIOS size is more than 32M, the physical address of EFS header will be complicated, like 0xfe020000 or 0xfc020000. So we make it simpler to allow to use relative address. This CL works with https://review.coreboot.org/c/coreboot/+/69852 TEST=Result image is binary same on amd/birman amd/majolica amd/gardina amd/mandolin Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-21 14:34:45 +01:00
/* efs_location is relative address now. */
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
switch (efs_location) {
amdfwtool: Remove comment "fallthrough" Fix the comment as "checkpatch" says. Change-Id: Ifa5d7de037aa7024779f3aa4a5d2f5033eed264a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71648 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-08 06:56:13 +01:00
case 0:
amdfwtool: Allow the location to be a relative address When the BIOS size is more than 32M, the physical address of EFS header will be complicated, like 0xfe020000 or 0xfc020000. So we make it simpler to allow to use relative address. This CL works with https://review.coreboot.org/c/coreboot/+/69852 TEST=Result image is binary same on amd/birman amd/majolica amd/gardina amd/mandolin Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-21 14:34:45 +01:00
case 0xFA0000:
case 0xF20000:
case 0xE20000:
case 0xC20000:
case 0x820000:
case 0x020000:
break;
case 0x7A0000:
case 0x720000:
case 0x620000:
case 0x420000:
/* Special cases for 8M. */
if (ctx.rom_size != 0x800000) {
fprintf(stderr, "Error: Invalid Directory location.\n");
fprintf(stderr, "%x is only for 8M image size.", efs_location);
return 1;
}
break;
case 0x3A0000:
case 0x320000:
case 0x220000:
/* Special cases for 4M. */
if (ctx.rom_size != 0x400000) {
fprintf(stderr, "Error: Invalid Directory location.\n");
fprintf(stderr, "%x is only for 4M image size.", efs_location);
return 1;
}
util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-07 22:16:39 +02:00
break;
default:
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: Invalid Directory location.\n");
fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n");
fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n");
amdfwtool: Allow the location to be a relative address When the BIOS size is more than 32M, the physical address of EFS header will be complicated, like 0xfe020000 or 0xfc020000. So we make it simpler to allow to use relative address. This CL works with https://review.coreboot.org/c/coreboot/+/69852 TEST=Result image is binary same on amd/birman amd/majolica amd/gardina amd/mandolin Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-11-21 14:34:45 +01:00
fprintf(stderr, " 0xFA0000, 0xF20000, 0xE20000, 0xC20000,\n");
fprintf(stderr, " 0x820000, 0x020000\n");
util/amdfwtool: update to allow building in any location For the verstage-on-PSP implementation, we need 2 additional copies of the AMD firmware tables at non-standard locations. These are for RW-A & RW-B fmap regions. This change allows us to build the AMD firmware tables into those regions. BUG=b:148767300 TEST=boot with psp_verstage, verify boot location Signed-off-by: Martin Roth <martin@coreboot.org> Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Change-Id: I7f841db8617b953dc671a9c12576145f85263581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-07 22:16:39 +02:00
return 1;
}
util/amdfwtool: Add option for directory location The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 22:16:04 +02:00
}
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
ctx.rom = malloc(ctx.rom_size);
if (!ctx.rom) {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: Failed to allocate memory\n");
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
return 1;
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
}
memset(ctx.rom, 0xFF, ctx.rom_size);
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
amdfwtool: Clean up the logic sequence of pointer growing When the EFS data is being packed, the pointer should be at EFS header. After that, it should be at body location. TEST=binary identical test on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: Ia81e2bdf9feb02971723f39e7f223b5055807cd8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-21 03:52:47 +01:00
romsig_offset = efs_location ? efs_location : AMD_ROMSIG_OFFSET;
set_current_pointer(&ctx, romsig_offset);
util/amdfwtool: Add option for directory location The AMD firmware directory can go in a number of different locations. This patch allows amdfwtool to write the directory correctly for those different locations. If the --location switch is not added to the command line, the default location at ROM base address + 0x20000 is used as before. BUG=b:65484600 TEST=Set PSP firmware location, compare amdfw.rom to previously built version. Verify new location pointers. Change-Id: Ief32e5e37d56088946b623d305c6e93bfd6abeaf Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-03 22:16:04 +02:00
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
amd_romsig = BUFF_OFFSET(ctx, romsig_offset);
util/amdfwtool: Clarify calculations with structures Replace the use of multiples of DWORDs with structures that describe the Embedded Firmware Table, and PSP directory headers & entries. TEST=Verify no difference in amdfw.rom for google/grunt build (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh), and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but was not verified. Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-24 00:42:46 +01:00
amd_romsig->signature = EMBEDDED_FW_SIGNATURE;
amd_romsig->imc_entry = 0;
amd_romsig->gec_entry = 0;
amd_romsig->xhci_entry = 0;
util/amdfwtool: Update with ROM size command line parameter Previously, the ROM size was passed into amdfwtool solely as a #define, meaning that all boards built with the tool would assume the same size ROM. This became a problem when the default rom for abuild was updated to be a board with a 256KB ROM. The temporary solution was to build amdfwtool individually for each board that needed it. This replaces that workaround by allowing the ROM size to be passed in as a command line parameter. - Add the -f | --flashsize option to accept a hex value for the ROM size. - Add checks to make sure the ROM size supplied is large enough. - Because the ROM size is not hardcoded, it needs to be passed to various functions. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0ca69cbba54797e0387a6e85935767b4136ef615 Reviewed-on: https://review.coreboot.org/17321 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 17:55:01 +01:00
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
if (cb_config.soc_id != PLATFORM_UNKNOWN) {
retval = set_efs_table(cb_config.soc_id, &cb_config, amd_romsig,
efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag);
amdfwtool: Call the set_efs_table for Stoneyridge Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-03 03:25:03 +01:00
if (retval) {
fprintf(stderr, "ERROR: Failed to initialize EFS table!\n");
return retval;
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
}
} else {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "WARNING: No SOC name specified.\n");
util/amdfwtool: Add support for EFS SPI values for F17h and F15h The Embedded Firmware Structure contains various SPI parameters for the PSP to program. This change adds support to amdfwtool for populating these values as well specifying SOC Family and Model. BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius. Change-Id: I87c4d44183ca65a5570de5e0c7f9b44aa6dd82f9 Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42566 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 18:18:15 +02:00
}
util/amdfwtool: use table-relative addressing in ISH case When the image slot header (ISH) is used, the addresses in the PSP and BIOS directory tables need to be relative to the beginning of the table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-29 23:10:45 +02:00
if (cb_config.need_ish)
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
ctx.address_mode = AMD_ADDR_REL_TAB;
amdfwtool: Add a flag to record the second gen instead of romsig This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-03 06:53:51 +02:00
else if (cb_config.second_gen)
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
ctx.address_mode = AMD_ADDR_REL_BIOS;
amdfwtool: Use relative address for EFS gen2 The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. The field additional_info in table header can tell if the absolute or relative address is used. Chips like Cezanne can run in both cases, so no problem comes up so far. The related change in psp_verstage has been uploaded. https://review.coreboot.org/c/coreboot/+/58316 The relative mode is the mode 1 of four address modes. The absolute mode is the mode 0. Later we will implement mode 2. Not sure if mode 3 is needed. It needs to be simple to work with psp_verstage change to make SOC Cezanne work quickly. This patch is defacto a subset of https://review.coreboot.org/c/coreboot/+/59308 which implements the framework of address mode and covers mode 0,1,2. Some hardcode value like 29 can be removed in 59308. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-04 13:03:10 +02:00
else
util/amdfwtool: Add amdfwread utility Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-14 22:59:12 +01:00
ctx.address_mode = AMD_ADDR_PHYSICAL;
amdfwtool: Report the address of EFS header and body The address mode is an internal mode which AMD FWs use. Regular developers don't have to know that. Just report the relative address every time. For the cases head and body are split, the address of body is also reported. Change-Id: I77d9aac0b3d996363341c1d2dae049ec344b39aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-04 09:38:28 +01:00
printf(" AMDFWTOOL Using firmware directory location of address: 0x%08x",
efs_location);
if (body_location != efs_location)
printf(" with a split body at: 0x%08x\n", body_location);
else
printf("\n");
amdfwtool: Use relative address for EFS gen2 The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. The field additional_info in table header can tell if the absolute or relative address is used. Chips like Cezanne can run in both cases, so no problem comes up so far. The related change in psp_verstage has been uploaded. https://review.coreboot.org/c/coreboot/+/58316 The relative mode is the mode 1 of four address modes. The absolute mode is the mode 0. Later we will implement mode 2. Not sure if mode 3 is needed. It needs to be simple to work with psp_verstage change to make SOC Cezanne work quickly. This patch is defacto a subset of https://review.coreboot.org/c/coreboot/+/59308 which implements the framework of address mode and covers mode 0,1,2. Some hardcode value like 29 can be removed in 59308. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-06-04 13:03:10 +02:00
amdfwtool: Clean up the logic sequence of pointer growing When the EFS data is being packed, the pointer should be at EFS header. After that, it should be at body location. TEST=binary identical test on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: Ia81e2bdf9feb02971723f39e7f223b5055807cd8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-21 03:52:47 +01:00
if (efs_location != body_location)
set_current_pointer(&ctx, body_location);
else
set_current_pointer(&ctx, romsig_offset + sizeof(embedded_firmware));
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
integrate_firmwares(&ctx, amd_romsig, amd_fw_table);
amdfwtool: Change the growing pointer with cautions Changing the pointer outside the function is not allowed. Check if it overflows everytime it changes. TEST=Binary identical on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I2c295b489d833201f1ba86a7759ea7dc0e1e672f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-17 04:01:07 +01:00
adjust_current_pointer(&ctx, 0, 0x10000U); /* TODO: is it necessary? */
amdfwtool: Upgrade "relative address" to four address modes Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-15 12:53:21 +01:00
ctx.current_table = 0;
util/amdfwtool: Streamline functions with context Replace variables and function arguments with a context that may be maintained and passed. Add macros to clarify the pointer math. Add functions to generate tables instead of relying on correct ordering and math. Use defined sizes for tables instead of arbitrary additions to an index. TEST=Verify no difference in amdfw.rom for google/grunt before and after, and verify a grunt build with PSP_COMBO=1 runs. Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 00:53:15 +01:00
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
/* If the tool is invoked with command-line options to keep the signed PSP
binaries separate, process the signed binaries first. */
if (signed_output_file && signed_start_addr)
process_signed_psp_firmwares(signed_output_file,
amd_psp_fw_table,
signed_start_addr,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
cb_config.soc_id);
util/amdfwtool: Add options to separate signed firmwares Add support for separating signed firmwares into another CBFS. If sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware is signed against AMD chain of trust and will be verified by PSP. If those firmware binaries are put outside FW_MAIN_[AB], vboot can skip redundant verification, improving overall verification time. BUG=b:206909680 TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS. Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 10:25:05 +01:00
amdfwtool: combo: Create the combo header earlier There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18 09:45:27 +02:00
if (cb_config.use_combo) {
psp_combo_dir = new_combo_dir(&ctx);
amdfwtool: combo: Add combo feature for BIOS table It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-18 09:54:47 +02:00
adjust_current_pointer(&ctx, 0, 0x1000U);
bhd_combo_dir = new_combo_dir(&ctx);
amdfwtool: combo: Create the combo header earlier There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18 09:45:27 +02:00
}
amdfwtool: Add flag for multi FW level to the struct amd_cb_config This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20 08:47:46 +02:00
if (cb_config.multi_level) {
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
/* Do 2nd PSP directory followed by 1st */
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
pspdir2 = new_psp_dir(&ctx, cb_config.multi_level);
integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) {
/* Create a copy of PSP Directory 2 in the backup slot B.
Related biosdir2_b copy will be created later. */
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
pspdir2_b = new_psp_dir(&ctx, cb_config.multi_level);
integrate_psp_firmwares(&ctx, pspdir2_b, NULL, NULL,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
amd_psp_fw_table, PSPL2_COOKIE, &cb_config);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
} else {
util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-08 22:19:55 +02:00
/*
* Either the platform is using only one slot or B is same as above
* directories for A. Skip creating pspdir2_b here to save flash space.
* Related biosdir2_b will be skipped automatically.
*/
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
pspdir2_b = NULL; /* More explicitly */
}
amdfwtool: Add flag for multi FW level to the struct amd_cb_config This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20 08:47:46 +02:00
pspdir = new_psp_dir(&ctx, cb_config.multi_level);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
integrate_psp_firmwares(&ctx, pspdir, pspdir2, pspdir2_b,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
amd_psp_fw_table, PSP_COOKIE, &cb_config);
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
} else {
/* flat: PSP 1 cookie and no pointer to 2nd table */
amdfwtool: Add flag for multi FW level to the struct amd_cb_config This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20 08:47:46 +02:00
pspdir = new_psp_dir(&ctx, cb_config.multi_level);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
integrate_psp_firmwares(&ctx, pspdir, NULL, NULL,
amdfwtool: Move soc_id to cb_config Save the soc_id into a global struct. Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25 15:37:29 +01:00
amd_psp_fw_table, PSP_COOKIE, &cb_config);
util/amdfwtool: Add multilevel PSP directory table Add the ability to generate two PSP directory table levels. The PSP is capable of supporting two levels, with the primary intended to remain pristine for the life of the system, and the second updatable. In the event the second becomes corrupted, the primary is still sufficient to allow a recovery of the other. This patch modifies no directory table structures currently in use. The soc or southbridge must pass an argument to force building the secondary table. BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-01 18:48:43 +02:00
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
amdfwtool: Separate two cases of combo and non-combo clearly If combo is used, fill the EFS header with address of COMBO header. If not, fill with address of PSP header. The old code fills with PSP headers all the time. Change-Id: I0057165aea553d9dc8e4e719e2804557229a0002 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66855 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18 09:52:31 +02:00
if (!cb_config.use_combo) {
fill_psp_directory_to_efs(amd_romsig, pspdir, &ctx, &cb_config);
} else {
amdfwtool: combo: Create the combo header earlier There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18 09:45:27 +02:00
fill_psp_directory_to_efs(amd_romsig, psp_combo_dir, &ctx, &cb_config);
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
/* 0 -Compare PSP ID, 1 -Compare chip family ID */
amdfwtool: combo: Create the combo header earlier There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18 09:45:27 +02:00
psp_combo_dir->entries[0].id_sel = 0;
psp_combo_dir->entries[0].id = get_psp_id(cb_config.soc_id);
psp_combo_dir->entries[0].lvl2_addr =
amdfwtool: Fill the address in EFS header as "relative to BIOS" If ctx.address_mode is "physical", it will keep as "physical". If ctx.address_mode is "relative to table", it will be changed as "relative to BIOS". Because the "current table" is the whole flash, the code worked well. TEST=Binary identical test on amd/birman amd/chausie amd/majolica amd/gardenia pcengines/apu2 amd/mandolin Change-Id: I9acb54cc5de149d8a705bb05bf351c44b7d3ced1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:14:53 +01:00
BUFF_TO_RUN_MODE(ctx, pspdir, AMD_ADDR_REL_BIOS);
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
amdfwtool: combo: Create the combo header earlier There will be a loop to set up the combo layout. The combo header only needs to be created once. This change is actually to move the creation of combo header outside of the loop. Change-Id: If6ba3d10dfc598133b9adbbb2b6658f356455608 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66854 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18 09:45:27 +02:00
fill_dir_header(psp_combo_dir, 1, PSP2_COOKIE, &ctx);
amdfwtool: Use command line option use-combo to decide if use combo The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-10 05:21:46 +01:00
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
if (have_bios_tables(amd_bios_table)) {
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
bios_directory_table *biosdir = NULL;
amdfwtool: Add flag for multi FW level to the struct amd_cb_config This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20 08:47:46 +02:00
if (cb_config.multi_level) {
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
/* Do 2nd level BIOS directory followed by 1st */
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
bios_directory_table *biosdir2 = NULL;
bios_directory_table *biosdir2_b = NULL;
biosdir2 = new_bios_dir(&ctx, cb_config.multi_level);
amdfwtool: Fix the parameter point to NULL instead of integer Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 10:47:07 +01:00
integrate_bios_firmwares(&ctx, biosdir2, NULL,
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
amd_bios_table, BHDL2_COOKIE, &cb_config);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
if (cb_config.recovery_ab) {
if (pspdir2_b != NULL) {
biosdir2_b = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir2_b, NULL,
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
amd_bios_table, BHDL2_COOKIE, &cb_config);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
}
add_psp_firmware_entry(&ctx, pspdir2, biosdir2,
AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT);
if (pspdir2_b != NULL)
add_psp_firmware_entry(&ctx, pspdir2_b, biosdir2_b,
AMD_FW_BIOS_TABLE, TABLE_ALIGNMENT);
} else {
biosdir = new_bios_dir(&ctx, cb_config.multi_level);
integrate_bios_firmwares(&ctx, biosdir, biosdir2,
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
amd_bios_table, BHD_COOKIE, &cb_config);
amdfwtool: Add support for AMD's BIOS A/B recovery feature The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-17 07:24:54 +02:00
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
} else {
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
/* flat: BHD1 cookie and no pointer to 2nd table */
amdfwtool: Add flag for multi FW level to the struct amd_cb_config This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-20 08:47:46 +02:00
biosdir = new_bios_dir(&ctx, cb_config.multi_level);
amdfwtool: Fix the parameter point to NULL instead of integer Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04 10:47:07 +01:00
integrate_bios_firmwares(&ctx, biosdir, NULL,
amdfwtool: Change the name of macros for 'BHD' Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-11 09:54:40 +02:00
amd_bios_table, BHD_COOKIE, &cb_config);
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
}
amdfwtool: combo: Add combo feature for BIOS table It is similar to PSP combo. Change-Id: If0523a4a0e1f31969e4bbaa6062dcc0f2d6da420 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-08-18 09:54:47 +02:00
if (!cb_config.use_combo) {
fill_bios_directory_to_efs(amd_romsig, biosdir, &ctx, &cb_config);
} else {
fill_bios_directory_to_efs(amd_romsig, bhd_combo_dir, &ctx, &cb_config);
bhd_combo_dir->entries[0].id_sel = 0;
bhd_combo_dir->entries[0].id = get_psp_id(cb_config.soc_id);
bhd_combo_dir->entries[0].lvl2_addr =
BUFF_TO_RUN_MODE(ctx, biosdir, AMD_ADDR_REL_BIOS);
fill_dir_header(bhd_combo_dir, 1, BHD2_COOKIE, &ctx);
}
util/amdfwtool: Update for Family 17h Add arguments for additional PSP blobs needed with Family 17h support, including the new AGESA binary loaders. Create a new type of structure and entry for a BIOS directory table, containing PMU code, microcode updates, as well as the BIOS initial code. Details on each of these items may be found in the AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors (NDA only, #55758). BUG=b:126593573 TEST=Used with WIP Picasso Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-19 21:45:31 +01:00
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666);
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
if (targetfd >= 0) {
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
uint32_t offset = efs_location;
uint32_t bytes = efs_location == body_location ?
ctx.current - offset : sizeof(*amd_romsig);
uint32_t ret_bytes;
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
ret_bytes = write(targetfd, BUFF_OFFSET(ctx, offset), bytes);
if (bytes != ret_bytes) {
amdfwtool: Use a variable to get the return value of write New Jenkins complaint about the original code that return value gets to nowhere. Fix that with a new variable. Change-Id: I8099b856ccb751dc380d0e95f5fe319cc3e2c6cc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45812 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29 11:33:17 +02:00
fprintf(stderr, "Error: Writing to file %s failed\n", output);
retval = 1;
}
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
close(targetfd);
} else {
amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01 11:05:43 +02:00
fprintf(stderr, "Error: could not open file: %s\n", output);
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
retval = 1;
}
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
amdfwtool: Change the variable name to body_location The dir_location and efs_location have the same meaning. Now the dir means body. Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-02 03:55:56 +01:00
if (efs_location != body_location) {
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
ssize_t bytes;
amdfwtool: Change .rom.efs to .rom and .rom to .rom.body To support 32M flash, the non-vboot also need to split amdfw. The amdfw.rom is the default filename added to CBFS. Keep the default filename and then we don't have to change all the CBFS definition. This is one of series of patches to support 32/64M flash. BUG=b:255374782 Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-22 14:08:18 +01:00
bytes = write_body(output, BUFF_OFFSET(ctx, body_location),
ctx.current - body_location, &ctx);
if (bytes != ctx.current - body_location) {
fprintf(stderr, "Error: Writing body\n");
util/amdfwtool: Write EFS and AMDFW body in separate files Add support to write EFS and AMDFW body to separate files. This is done through passing an optional --body-location parameter to the amdfwtool. If that option is not passed, then EFS will be written in the same file as the AMDFW body. This will help to keep the minimum data to be loaded/mapped from CBFS in PSP verstage. BUG=None TEST=Build and boot to OS in Skyrim. Change-Id: I79325c81394cf8a0c663752d094adf6660896127 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70778 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-02 23:53:54 +01:00
retval = 1;
}
}
amdfwtool: Add universal cleanup function Change-Id: Icc0cb79c06614aa2976d250dc73b8dc4040fd28c Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-19 06:02:52 +01:00
amdfwtool_cleanup(&ctx);
util/amdfwtool: unify return values, verify the file open - Return an error if the specified file could not be opened. To do this cleanly, the return value was added. - Since there's now a unified return value, use it where it makes sense. - Don't return an error from --help. If you've asked for usage, it's not an error. Change-Id: I7c712d1e1927c2d4957b044b87ad26475b7a0e3b Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17324 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-11-08 19:22:12 +01:00
return retval;
amdfwtool: Add amdfwtool to combine AMD firmwares Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/12419 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-17 15:57:39 +01:00
}