2019-05-10 15:52:00 +02:00
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# Supermicro X11SSH-TF
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This section details how to run coreboot on the [Supermicro X11SSH-TF].
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## Required proprietary blobs
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* [Intel FSP2.0]
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* Intel ME
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## Flashing coreboot
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The board can be flashed externally using *some* programmers.
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The CH341 was found working, while Dediprog won't detect the chip.
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For more details have a look at the [flashing tutorial].
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The flash IC can be found between the two PCIe slots near the southbridge:
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mb/supermicro: restructure x11ssh-tf to represent a x11 board series
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.
There are about 20 boards that can be added, if there is a community for
testing.
To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.
It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").
The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.
X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.
Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.
Documentation is reworked in CB:35547
Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 16:31:50 +02:00
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![](x11ssh-tf_flash.jpg)
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2019-05-10 15:52:00 +02:00
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## BMC (IPMI)
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This board has an ASPEED [AST2400], which has BMC functionality. The
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BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the
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mainboard near the [AST2400]. This chip is an [MX25L25635F].
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## Known issues
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- Intel SGX causes secondary APs to crash (disabled for now).
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- Tianocore doesn't work with Aspeed NGI, as it's text mode only.
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2019-09-19 08:51:24 +02:00
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- SMBus / I2C does not work (interrupt timeout)
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2019-05-10 15:52:00 +02:00
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## Tested and working
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- USB ports
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- M.2 2280 NVMe slot
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- 2x 10GB Ethernet
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- SATA
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- RS232
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- VGA on Aspeed
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- Super I/O initialisation
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- ECC DRAM detection
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- PCIe slots
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- TPM on TPM expansion header
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- BMC (IPMI)
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Kaby Lake |
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+------------------+--------------------------------------------------+
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| PCH | Intel C236 |
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+------------------+--------------------------------------------------+
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| Super I/O | ASPEED AST2400 |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel SPS (server version of the ME) |
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+------------------+--------------------------------------------------+
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| Coprocessor | ASPEED AST2400 |
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+------------------+--------------------------------------------------+
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```
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## Extra links
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- [Board manual]
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[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
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[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
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[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
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mb/supermicro: restructure x11ssh-tf to represent a x11 board series
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.
There are about 20 boards that can be added, if there is a community for
testing.
To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.
It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").
The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.
X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.
Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.
Documentation is reworked in CB:35547
Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-18 16:31:50 +02:00
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[flashing tutorial]: ../../../../flash_tutorial/ext_power.md
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[Intel FSP2.0]: ../../../../soc/intel/fsp/index.md
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2019-05-10 15:52:00 +02:00
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[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF
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