2011-02-22 15:35:05 +01:00
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
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GIT := $ ( shell [ - d " $ (top)/.git " ] && command - v git )
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#######################################################################
# misleadingly named, this is the coreboot version
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export KERNELVERSION := $ ( strip $ ( if $ ( GIT ), \
$ ( shell git describe -- dirty -- always || git describe ), \
4.0 $ ( KERNELREVISION )))
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#######################################################################
# Basic component discovery
MAINBOARDDIR = $ ( call strip_quotes , $ ( CONFIG_MAINBOARD_DIR ))
export MAINBOARDDIR
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## Final build results, which CBFSTOOL uses to create the final
## rom image file, are placed under $(objcbfs).
## These typically have suffixes .debug .elf .bin and .map
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export objcbfs := $ ( obj ) / cbfs / $ ( call strip_quotes , $ ( CONFIG_CBFS_PREFIX ))
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## Based on the active configuration, Makefile conditionally collects
## the required assembly includes and saves them in a file.
## Such files that do not have a clear one-to-one relation to a source
## file under src/ are placed and built under $(objgenerated)
export objgenerated := $ ( obj ) / generated
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#######################################################################
# root rule to resolve if in build mode (ie. configuration exists)
real - target : $ ( obj ) / config . h coreboot
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coreboot : build - dirs $ ( obj ) / coreboot . rom $ ( obj ) / cbfstool $ ( obj ) / rmodtool
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#######################################################################
# our phony targets
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PHONY += clean - abuild coreboot lint lint - stable build - dirs
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#######################################################################
# root source directories of coreboot
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subdirs - y := src / lib src / console src / device src / ec src / southbridge src / soc
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subdirs - y += src / northbridge src / superio src / drivers src / cpu src / vendorcode
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subdirs - y += util / cbfstool util / sconfig util / nvramtool util / broadcom
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subdirs - y += src / arch / arm src / arch / arm64 src / arch / mips src / arch / riscv
subdirs - y += src / arch / x86
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subdirs - y += src / mainboard / $ ( MAINBOARDDIR )
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subdirs - y += site - local
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#######################################################################
# Add source classes and their build options
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classes - y := ramstage romstage bootblock smm smmstub cpu_microcode verstage secmon
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# Add dynamic classes for rmodules
$ ( foreach supported_arch , $ ( ARCH_SUPPORTED ), \
$ ( eval $ ( call define_class , rmodules_ $ ( supported_arch ), $ ( supported_arch ))))
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#######################################################################
# Helper functions for various file placement matters
#
# int-add: adds an arbitrary number of space-separated integers in
# all formats understood by printf(1)
# int-align: align $1 to $2 units
# file-size: returns the filesize of the given file
_toint = $ ( shell printf " %d " $ 1 )
_int - add2 = $ ( shell expr $ ( call _toint , $ 1 ) + $ ( call _toint , $ 2 ))
int - add = $ ( if $ ( filter 1 , $ ( words $ 1 )), $ ( strip $ 1 ), $ ( call int - add , $ ( call _int - add2 , $ ( word 1 , $ 1 ), $ ( word 2 , $ 1 )) $ ( wordlist 3 , $ ( words $ 1 ), $ 1 )))
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int - align = $ ( shell A = $ ( call _toint , $ 1 ) B = $ ( call _toint , $ 2 ); expr $$A + \ ( \ ( $$B - \ ( $$A % $$B \ ) \ ) % $$B \ ) )
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file - size = $ ( shell cat $ 1 | wc - c )
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#######################################################################
# Helper functions for ramstage postprocess
spc :=
spc +=
$ ( spc ) :=
$ ( spc ) +=
# files-in-dir-recursive,dir,files
files - in - dir - recursive = $ ( filter $ ( 1 ) % , $ ( 2 ))
# parent-dir,dir/
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parent - dir = $ ( dir $ ( if $ ( patsubst /% ,, $ ( 1 )),, / ) $ ( subst $ ( ), / , $ ( strip $ ( subst / , , $ ( 1 )))))
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# filters out exactly the directory specified
# filter-out-dir,dir_to_keep,dirs
filter - out - dir = $ ( filter - out $ ( 1 ), $ ( 2 ))
# filters out dir_to_keep and all its parents
# filter-out-dirs,dir_to_keep,dirs
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filter - out - dirs = $ ( if $ ( filter - out ./ / , $ ( 1 )), $ ( call filter - out - dirs , $ ( call parent - dir , $ ( 1 )), $ ( call filter - out - dir , $ ( 1 ), $ ( 2 ))), $ ( call filter - out - dir , $ ( 1 ), $ ( 2 )))
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# dir-wildcards,dirs
dir - wildcards = $ ( addsuffix % , $ ( 1 ))
# files-in-dir,dir,files
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files - in - dir = $ ( filter - out $ ( call dir - wildcards , $ ( call filter - out - dirs , $ ( 1 ), $ ( sort $ ( dir $ ( 2 ))))), $ ( call files - in - dir - recursive , $ ( 1 ), $ ( 2 )))
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#######################################################################
# reduce command line length by linking the objects of each
# directory into an intermediate file
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ramstage - postprocess = $ $ ( eval DEPENDENCIES += $ $ ( addsuffix . d , $ $ ( basename $ ( 1 )))) \
$ ( foreach d , $ ( sort $ ( dir $ ( filter - out %. ld , $ ( 1 )))), \
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$ ( eval $ ( d ) ramstage . o : $ ( call files - in - dir , $ ( d ), $ ( filter - out %. ld , $ ( 1 ))); $ $ ( LD_ramstage ) - o $ $ @ - r $ $ ^ ) \
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$ ( eval ramstage - objs := $ ( d ) ramstage . o $ ( filter - out $ ( filter - out %. ld , $ ( call files - in - dir , $ ( d ), $ ( 1 ))), $ ( ramstage - objs ))))
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bootblock - generic - ccopts += - D__PRE_RAM__ - D__BOOTBLOCK__
romstage - generic - ccopts += - D__PRE_RAM__ - D__ROMSTAGE__
ramstage - generic - ccopts += - D__RAMSTAGE__
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ifeq ( $ ( CONFIG_TRACE ), y )
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ramstage - c - ccopts += - finstrument - functions
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endif
Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.
See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.
To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.
For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/
Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19 01:23:28 +01:00
ifeq ( $ ( CONFIG_COVERAGE ), y )
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ramstage - c - ccopts += - fprofile - arcs - ftest - coverage
Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.
See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.
To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.
For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/
Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19 01:23:28 +01:00
endif
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# try to fetch non-optional submodules if the source is under git
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forgetthis := $ ( if $ ( GIT ), $ ( shell git submodule update -- init ))
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ifeq ( $ ( CONFIG_USE_BLOBS ), y )
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# this is necessary because 3rdparty is update=none, and so is ignored
# unless explicitly requested and enabled through --checkout
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forgetthis := $ ( if $ ( GIT ), $ ( shell git submodule update -- init -- checkout 3 rdparty ))
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endif
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ramstage - c - deps := $ $ ( OPTION_TABLE_H )
romstage - c - deps := $ $ ( OPTION_TABLE_H )
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verstage - c - deps := $ $ ( OPTION_TABLE_H )
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bootblock - c - deps := $ $ ( OPTION_TABLE_H )
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# Add handler to copy linker scripts
define generic - objs_ld_template_gen
de $ ( EMPTY ) fine $ ( 1 ) - objs_ld_template
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$ $ ( call src - to - obj , $ 1 , $ $ ( 1 ) . ld ) : $ $ ( 1 ) . ld $ ( obj ) / config . h
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@ printf " CP $ $ $ $ (subst $ $ $ $ (obj)/,, $ $ $ $ (@)) \n "
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$ $ ( CC_ $ ( 1 )) $ $ ( CPPFLAGS_ $ ( 1 )) $ ( $ ( 1 ) - ld - ccopts ) $ ( PREPROCESS_ONLY ) - include $ ( obj ) / config . h $ $ $ $ < > $ $ $ $ @. tmp
mv $ $ $ $ @. tmp $ $ $ $ @
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en $ ( EMPTY ) def
endef
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# Add handler to add no rules for manual files
define generic - objs_manual_template_gen
# do nothing
endef
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#######################################################################
# Add handler to compile ACPI's ASL
define ramstage - objs_asl_template
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$ $ ( call src - to - obj , ramstage , $ ( 1 ) . asl ) : $ ( 1 ) . asl $ ( obj ) / config . h
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@ printf " IASL $ $ (subst $ (top)/,, $ $ (@)) \n "
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$ ( CC_ramstage ) - x assembler - with - cpp - E - MMD - MT $ $ ( @ ) $ $ ( CPPFLAGS_ramstage ) - D__ACPI__ - P - include $ ( src ) / include / kconfig . h - I $ ( obj ) - I $ ( src ) - I $ ( src ) / include - I $ ( src ) / arch / $ ( ARCHDIR - $ ( ARCH - ramstage - y )) / include - I $ ( src ) / mainboard / $ ( MAINBOARDDIR ) $ $ < - o $ $ @
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cd $ $ ( dir $ $ @ ); $ ( IASL ) - p $ $ ( notdir $ $ @ ) - tc $ $ ( notdir $ $ @ )
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mv $ $ ( basename $ $ @ ) . hex $ $ ( basename $ $ @ ) . c
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$ ( CC_ramstage ) $ $ ( CFLAGS_ramstage ) $ $ ( CPPFLAGS_ramstage ) $ $ ( if $ $ ( subst dsdt ,, $ $ ( basename $ $ ( notdir $ ( 1 )))), - DAmlCode = AmlCode_ $ $ ( basename $ $ ( notdir $ ( 1 )))) - c - o $ $ @ $ $ ( basename $ $ @ ) . c
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# keep %.o: %.c rule from catching the temporary .c file after a make clean
mv $ $ ( basename $ $ @ ) . c $ $ ( basename $ $ @ ) . hex
endef
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#######################################################################
# Parse plaintext cmos defaults into binary format
# arg1: source file
# arg2: binary file name
cbfs - files - processor - nvramtool = \
$ ( eval $ ( 2 ) : $ ( 1 ) $ ( src ) / mainboard / $ ( MAINBOARDDIR ) / cmos . layout | $ ( objutil ) / nvramtool / nvramtool ; \
printf " CREATE $ (2) (from $ (1)) \n " ; $ ( objutil ) / nvramtool / nvramtool - y $ ( src ) / mainboard / $ ( MAINBOARDDIR ) / cmos . layout - D $ ( 2 ) . tmp - p $ ( 1 ) && mv $ ( 2 ) . tmp $ ( 2 ))
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#######################################################################
# Link VSA binary to ELF-ish stage
# arg1: source file
# arg2: binary file name
cbfs - files - processor - vsa = \
$ ( eval $ ( 2 ) : $ ( 1 ) ; \
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
printf " CREATE $ (2) (from $ (1)) \n " ; $ ( OBJCOPY_ramstage ) -- set - start 0x20 -- adjust - vma 0x60000 - I binary - O elf32 - i386 - B i386 $ ( 1 ) $ ( 2 ) . tmp && $ ( LD_ramstage ) - m elf_i386 - e 0x60020 -- section - start . data = 0x60000 $ ( 2 ) . tmp - o $ ( 2 ))
2012-04-30 23:15:17 +02:00
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#######################################################################
# Add handler for arbitrary files in CBFS
$ ( call add - special - class , cbfs - files )
cbfs - files - handler = \
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$ ( eval tmp - cbfs - method := $ ( word 2 , $ ( subst : , , $ ( $ ( 2 ) - file )))) \
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$ ( eval $ ( 2 ) - file := $ ( call strip_quotes , $ ( word 1 , $ ( subst : , , $ ( $ ( 2 ) - file ))))) \
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$ ( if $ ( wildcard $ ( 1 ) $ ( $ ( 2 ) - file )), \
$ ( eval tmp - cbfs - file := $ ( wildcard $ ( 1 ) $ ( $ ( 2 ) - file ))), \
$ ( eval tmp - cbfs - file := $ ( $ ( 2 ) - file ))) \
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$ ( if $ ( strip $ ( $ ( 2 ) - required )), \
$ ( if $ ( wildcard $ ( tmp - cbfs - file )),, \
$ ( info This build configuration requires $ ( $ ( 2 ) - required )) \
$ ( eval FAILBUILD := 1 ) \
)) \
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$ ( if $ ( strip $ ( $ ( 2 ) - align )), \
$ ( if $ ( strip $ ( $ ( 2 ) - position )), \
$ ( info ERROR : It is not allowed to specify both alignment and position for $ ( $ ( 2 ) - file )) \
$ ( eval FAILBUILD := 1 ) \
)) \
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$ ( if $ ( tmp - cbfs - method ), \
$ ( eval tmp - old - cbfs - file := $ ( tmp - cbfs - file )) \
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$ ( eval tmp - cbfs - file := $ ( shell mkdir - p $ ( obj ) / mainboard / $ ( MAINBOARDDIR ); mktemp $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / cbfs - file . XXXXXX ) . out ) \
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$ ( call cbfs - files - processor - $ ( tmp - cbfs - method ), $ ( tmp - old - cbfs - file ), $ ( tmp - cbfs - file ))) \
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$ ( eval cbfs - files += $ ( tmp - cbfs - file ) | $ ( 2 ) | $ ( $ ( 2 ) - type ) | $ ( $ ( 2 ) - compression ) | $ ( strip $ ( $ ( 2 ) - position )) | $ ( $ ( 2 ) - align )) \
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$ ( eval $ ( 2 ) - name := ) \
$ ( eval $ ( 2 ) - type := ) \
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$ ( eval $ ( 2 ) - compression := ) \
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$ ( eval $ ( 2 ) - position := ) \
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$ ( eval $ ( 2 ) - required := ) \
$ ( eval $ ( 2 ) - align := )
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#######################################################################
# a variety of flags for our build
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CBFS_COMPRESS_FLAG := none
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ifeq ( $ ( CONFIG_COMPRESS_RAMSTAGE ), y )
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CBFS_COMPRESS_FLAG := LZMA
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endif
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CBFS_PAYLOAD_COMPRESS_FLAG := none
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ifeq ( $ ( CONFIG_COMPRESSED_PAYLOAD_LZMA ), y )
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CBFS_PAYLOAD_COMPRESS_FLAG := LZMA
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endif
ifneq ( $ ( CONFIG_LOCALVERSION ), " " )
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export COREBOOT_EXTRA_VERSION := - $ ( call strip_quotes , $ ( CONFIG_LOCALVERSION ))
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endif
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CPPFLAGS_common := - Isrc - Isrc / include - I $ ( obj )
CPPFLAGS_common += - Isrc / device / oprom / include
CPPFLAGS_common += - include $ ( src ) / include / kconfig . h
2011-02-22 15:35:05 +01:00
2014-04-23 02:06:43 +02:00
CFLAGS_common += - pipe - g - nostdinc
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
CFLAGS_common += - nostdlib - Wall - Wundef - Wstrict - prototypes - Wmissing - prototypes
CFLAGS_common += - Wwrite - strings - Wredundant - decls - Wno - trigraphs
2015-04-08 10:53:39 +02:00
CFLAGS_common += - Wstrict - aliasing - Wshadow
ifeq ( $ ( CONFIG_COMPILER_GCC ), y )
# cf. commit f69a99db (coreboot: x86: enable gc-sections)
CFLAGS_common += - Wno - unused - but - set - variable
endif
2011-02-22 15:35:05 +01:00
ifeq ( $ ( CONFIG_WARNINGS_ARE_ERRORS ), y )
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
CFLAGS_common += - Werror
2011-02-22 15:35:05 +01:00
endif
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
CFLAGS_common += - fno - common - ffreestanding - fno - builtin - fomit - frame - pointer
2014-04-23 02:06:43 +02:00
ifneq ( $ ( GDB_DEBUG ),)
2015-03-15 00:21:17 +01:00
CFLAGS_common += - Og
2014-04-23 02:06:43 +02:00
else
CFLAGS_common += - Os
endif
2013-06-19 16:16:05 +02:00
additional - dirs := $ ( objutil ) / cbfstool $ ( objutil ) / romcc $ ( objutil ) / ifdtool \
2014-09-08 23:28:17 +02:00
$ ( objutil ) / ifdfake $ ( objutil ) / options $ ( objutil ) / fletcher \
2014-06-14 01:09:49 +02:00
$ ( objutil ) / cbootimage $ ( objutil ) / bimgtool
2011-02-22 15:35:05 +01:00
#######################################################################
# generate build support files
$ ( obj ) / build . h : . xcompile
@ printf " GEN build.h \n "
rm - f $ ( obj ) / build . h
2015-02-13 03:32:41 +01:00
util / genbuild_h / genbuild_h . sh > $ ( obj ) / build . ht
2011-02-22 15:35:05 +01:00
mv $ ( obj ) / build . ht $ ( obj ) / build . h
2012-04-19 11:00:06 +02:00
build - dirs :
mkdir - p $ ( objcbfs ) $ ( objgenerated )
2011-02-22 15:35:05 +01:00
#######################################################################
# Build the tools
2014-07-10 09:42:03 +02:00
CBFSTOOL := $ ( objutil ) / cbfstool / cbfstool
RMODTOOL := $ ( objutil ) / cbfstool / rmodtool
2011-02-22 15:35:05 +01:00
2014-07-10 09:42:03 +02:00
$ ( obj ) / cbfstool : $ ( CBFSTOOL )
2011-02-22 15:35:05 +01:00
cp $ < $ @
2014-07-10 09:42:03 +02:00
$ ( obj ) / rmodtool : $ ( RMODTOOL )
2014-03-10 22:13:58 +01:00
cp $ < $ @
2011-02-22 15:35:05 +01:00
_WINCHECK = $ ( shell uname - o 2 > / dev / null )
STACK =
ifeq ( $ ( _WINCHECK ), Msys )
STACK =- Wl , -- stack , 16384000
endif
ifeq ( $ ( _WINCHECK ), Cygwin )
STACK =- Wl , -- stack , 16384000
endif
2014-05-17 19:05:56 +02:00
# this allows ccache to prepend itself
# (ccache handling happens first)
ROMCC_BIN = $ ( objutil ) / romcc / romcc
ROMCC ? = $ ( ROMCC_BIN )
$ ( ROMCC_BIN ) : $ ( top ) / util / romcc / romcc . c
2011-02-22 15:35:05 +01:00
@ printf " HOSTCC $ (subst $ (obj)/,, $ (@)) (this may take a while) \n "
@ # Note: Adding -O2 here might cause problems. For details see:
@ # http://www.coreboot.org/pipermail/coreboot/2010-February/055825.html
$ ( HOSTCC ) - g $ ( STACK ) - Wall - o $ @ $ <
2012-08-16 23:05:42 +02:00
IFDTOOL := $ ( objutil ) / ifdtool / ifdtool
$ ( IFDTOOL ) : $ ( top ) / util / ifdtool / ifdtool . c
@ printf " HOSTCC $ (subst $ (obj)/,, $ (@)) \n "
$ ( HOSTCC ) $ ( HOSTCFLAGS ) - o $ @ $ <
2013-06-19 16:16:05 +02:00
IFDFAKE := $ ( objutil ) / ifdfake / ifdfake
$ ( IFDFAKE ) : $ ( top ) / util / ifdfake / ifdfake . c
@ printf " HOSTCC $ (subst $ (obj)/,, $ (@)) \n "
$ ( HOSTCC ) $ ( HOSTCFLAGS ) - o $ @ $ <
2014-08-11 01:09:15 +02:00
FLETCHER := $ ( objutil ) / fletcher / fletcher
$ ( FLETCHER ) : $ ( top ) / util / fletcher / fletcher . c
@ printf " HOSTCC $ (subst $ (obj)/,, $ (@)) \n "
$ ( HOSTCC ) $ ( HOSTCFLAGS ) - o $ @ $ <
2014-09-08 23:28:17 +02:00
CBOOTIMAGE := $ ( objutil ) / cbootimage / cbootimage
2014-09-27 11:37:46 +02:00
subdirs - y += util / nvidia
2014-09-08 23:28:17 +02:00
2014-06-14 01:09:49 +02:00
BIMGTOOL := $ ( objutil ) / bimgtool / bimgtool
$ ( BIMGTOOL ) : $ ( top ) / util / bimgtool / bimgtool . c
@ printf " HOSTCC $ (subst $ (obj)/,, $ (@)) \n "
$ ( HOSTCC ) $ ( HOSTCFLAGS ) - o $ @ $ <
2011-02-22 15:35:05 +01:00
#######################################################################
# needed objects that every mainboard uses
# Creation of these is architecture and mainboard independent
$ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / static . c : $ ( src ) / mainboard / $ ( MAINBOARDDIR ) / devicetree . cb $ ( objutil ) / sconfig / sconfig
@ printf " SCONFIG $ (subst $ (src)/,, $ (<)) \n "
mkdir - p $ ( obj ) / mainboard / $ ( MAINBOARDDIR )
$ ( objutil ) / sconfig / sconfig $ ( MAINBOARDDIR ) $ ( obj ) / mainboard / $ ( MAINBOARDDIR )
ramstage - y += $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / static . c
Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage
We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.
So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
#ifndef __PRE_RAM__
.ops = 0,
#endif
.bus = &_dev7_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
.enabled = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1ae0,
.subsystem_device = 0xc000,
.link_list = NULL,
.sibling = &_dev22,
#ifndef __PRE_RAM__
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_10,
.next=&_dev22
};
Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 01:47:25 +02:00
romstage - y += $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / static . c
2011-02-22 15:35:05 +01:00
$ ( objutil ) /%. o : $ ( objutil ) /%. c
@ printf " HOSTCC $ (subst $ (objutil)/,, $ (@)) \n "
$ ( HOSTCC ) - MMD - I $ ( subst $ ( objutil ) / , util / , $ ( dir $ < )) - I $ ( dir $ < ) $ ( HOSTCFLAGS ) - c - o $ @ $ <
2011-05-21 01:08:12 +02:00
$ ( obj ) /%. ramstage . o $ ( abspath $ ( obj )) /%. ramstage . o : $ ( obj ) /%. c $ ( obj ) / config . h $ ( OPTION_TABLE_H )
2011-02-22 15:35:05 +01:00
@ printf " CC $ (subst $ (obj)/,, $ (@)) \n "
2014-11-06 23:50:22 +01:00
$ ( CC_ramstage ) - MMD $ ( CFLAGS_ramstage ) $ ( CPPFLAGS_ramstage ) $ ( ramstage - c - ccopts ) - c - o $ @ $ <
2011-02-22 15:35:05 +01:00
Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage
We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.
So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
#ifndef __PRE_RAM__
.ops = 0,
#endif
.bus = &_dev7_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
.enabled = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1ae0,
.subsystem_device = 0xc000,
.link_list = NULL,
.sibling = &_dev22,
#ifndef __PRE_RAM__
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_10,
.next=&_dev22
};
Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 01:47:25 +02:00
$ ( obj ) /%. romstage . o $ ( abspath $ ( obj )) /%. romstage . o : $ ( obj ) /%. c $ ( obj ) / config . h $ ( OPTION_TABLE_H )
@ printf " CC $ (subst $ (obj)/,, $ (@)) \n "
2014-11-06 23:50:22 +01:00
$ ( CC_romstage ) - MMD $ ( CFLAGS_romstage ) $ ( CPPFLAGS_romstage ) $ ( romstage - c - ccopts ) - c - o $ @ $ <
Make the device tree available in the rom stage
We thought about two ways to do this change. The way we decided to try
was to
1. drop all ops from devices in romstage
2. constify all devices in romstage (make them read-only) so we can
compile static.c into romstage
3. the device tree "devices" can be used to read configuration from
the device tree (and nothing else, really)
4. the device tree devices are accessed through struct device * in
romstage only. device_t stays the typedef to int in romstage
5. Use the same static.c file in ramstage and romstage
We declare structs as follows:
ROMSTAGE_CONST struct bus dev_root_links[];
ROMSTAGE_CONST is const in romstage and empty in ramstage; This
forces all of the device tree into the text area.
So a struct looks like this:
static ROMSTAGE_CONST struct device _dev21 = {
#ifndef __PRE_RAM__
.ops = 0,
#endif
.bus = &_dev7_links[0],
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1c,3)}}},
.enabled = 0,
.on_mainboard = 1,
.subsystem_vendor = 0x1ae0,
.subsystem_device = 0xc000,
.link_list = NULL,
.sibling = &_dev22,
#ifndef __PRE_RAM__
.chip_ops = &southbridge_intel_bd82x6x_ops,
#endif
.chip_info = &southbridge_intel_bd82x6x_info_10,
.next=&_dev22
};
Change-Id: I722454d8d3c40baf7df989f5a6891f6ba7db5727
Signed-off-by: Ronald G. Minnich <rminnich@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1398
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 01:47:25 +02:00
2013-01-31 18:09:24 +01:00
$ ( obj ) /%. bootblock . o $ ( abspath $ ( obj )) /%. bootblock . o : $ ( obj ) /%. c $ ( obj ) / config . h $ ( OPTION_TABLE_H )
@ printf " CC $ (subst $ (obj)/,, $ (@)) \n "
2014-11-06 23:50:22 +01:00
$ ( CC_bootblock ) - MMD $ ( CFLAGS_bootblock ) $ ( CPPFLAGS_bootblock ) $ ( bootblock - c - ccopts ) - c - o $ @ $ <
2013-01-31 18:09:24 +01:00
2011-02-22 15:35:05 +01:00
#######################################################################
# Clean up rules
clean - abuild :
rm - rf coreboot - builds
clean - for - update - target :
2014-04-22 19:41:05 +02:00
rm - f $ ( obj ) / ramstage * $ ( obj ) / coreboot . romstage $ ( obj ) / coreboot . pre * $ ( obj ) / coreboot . bootblock $ ( obj ) / coreboot . a
2011-02-22 15:35:05 +01:00
rm - rf $ ( obj ) / bootblock * $ ( obj ) / romstage * $ ( obj ) / location .*
rm - f $ ( obj ) / option_table .* $ ( obj ) / crt0 . S $ ( obj ) / ldscript
rm - f $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / static . c $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / config . py $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / static . dot
rm - f $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / crt0 . s $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / crt0 . disasm
rm - f $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / romstage . inc
rm - f $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / bootblock .* $ ( obj ) / mainboard / $ ( MAINBOARDDIR ) / dsdt .*
rm - f $ ( obj ) / cpu / x86 / smm / smm_bin . c $ ( obj ) / cpu / x86 / smm / smm .* $ ( obj ) / cpu / x86 / smm / smm
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
$ ( MAKE ) - C payloads / external / SeaBIOS - f Makefile . inc clean OUT = $ ( abspath $ ( obj )) HOSTCC = " $ (HOSTCC) " CC = " $ (CC_x86_32) " LD = " $ (LD_x86_32) "
2011-02-22 15:35:05 +01:00
clean - target :
rm - f $ ( obj ) / coreboot *
#######################################################################
# Development utilities
printcrt0s :
@ echo crt0s = $ ( crt0s )
@ echo ldscripts = $ ( ldscripts )
update :
dongle . py - c / dev / term / 1 $ ( obj ) / coreboot . rom EOF
2012-02-25 19:42:59 +01:00
lint lint - stable :
2012-09-28 13:38:37 +02:00
FAILED = 0 ; LINTLOG = `mktemp .tmpconfig.lintXXXXX` ; \
2012-02-25 19:42:59 +01:00
for script in util / lint / $ @-* ; do \
2011-02-22 15:35:05 +01:00
echo ; echo `basename $$script` ; \
grep " ^# DESCR: " $$script | sed " s,.*DESCR: *,, " ; \
echo ======== ; \
$$script > $$LINTLOG ; \
2012-03-09 23:02:09 +01:00
if [ `cat $$LINTLOG | wc -l` - eq 0 ]; then \
2011-02-22 15:35:05 +01:00
printf " success \n \n " ; \
else \
echo test failed : ; \
cat $$LINTLOG ; \
rm - f $$LINTLOG ; \
FAILED = $ $ (( $$FAILED + 1 )); \
fi ; \
echo ======== ; \
done ; \
2014-08-10 19:15:04 +02:00
test $$FAILED - eq 0 || { echo " ERROR: $ $FAILED test(s) failed. " ; rm - f $$LINTLOG && exit 1 ; }; \
2011-02-22 15:35:05 +01:00
rm - f $$LINTLOG
2011-05-16 17:32:28 +02:00
2011-06-05 15:15:49 +02:00
gitconfig :
2015-03-04 15:03:05 +01:00
[ - d . git ]
2012-10-22 10:29:37 +02:00
mkdir - p . git / hooks
2012-08-10 09:44:02 +02:00
for hook in commit - msg pre - commit ; do \
if [ util / gitconfig / $$hook - nt . git / hooks / $$hook - o \
! - x . git / hooks / $$hook ]; then \
cp util / gitconfig / $$hook . git / hooks / $$hook ; \
chmod + x . git / hooks / $$hook ; \
fi ; \
done
2013-01-03 17:26:09 +01:00
git config remote . origin . push HEAD : refs / for / master
2011-06-05 15:15:49 +02:00
( git config -- global user . name >/ dev / null && git config -- global user . email >/ dev / null ) || ( printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email@example.com\n' ; exit 1 )
2015-03-13 22:50:22 +01:00
crossgcc : crossgcc - i386 crossgcc - x64 crossgcc - arm crossgcc - aarch64 crossgcc - mips crossgcc - riscv
2011-06-09 05:06:25 +02:00
2015-03-13 22:50:22 +01:00
. PHONY : crossgcc - i386 crossgcc - x64 crossgcc - arm crossgcc - aarch64 crossgcc - mips crossgcc - riscv
2013-11-01 17:40:39 +01:00
crossgcc - i386 : clean - for - update
$ ( MAKE ) - C util / crossgcc build - i386 - without - gdb
2015-03-13 22:50:22 +01:00
crossgcc - x64 : clean - for - update
$ ( MAKE ) - C util / crossgcc build - x64 - without - gdb
2013-11-01 17:40:39 +01:00
crossgcc - arm : clean - for - update
$ ( MAKE ) - C util / crossgcc build - armv7a - without - gdb
2014-11-19 18:36:37 +01:00
crossgcc - aarch64 : clean - for - update
$ ( MAKE ) - C util / crossgcc build - aarch64 - without - gdb
2015-02-27 23:41:15 +01:00
crossgcc - mips : clean - for - update
$ ( MAKE ) - C util / crossgcc build - mips - without - gdb
2013-11-01 17:40:39 +01:00
2015-03-07 10:57:25 +01:00
crossgcc - riscv : clean - for - update
$ ( MAKE ) - C util / crossgcc build - riscv - without - gdb
2015-02-27 23:41:15 +01:00
2015-03-13 22:50:22 +01:00
crosstools : crosstools - i386 crosstools - x64 crosstools - arm crosstools - aarch64 crosstools - mips crosstools - riscv
2015-03-07 10:57:25 +01:00
2015-03-13 22:50:22 +01:00
. PHONY : crosstools - i386 crosstools - x64 crosstools - arm crosstools - aarch64 crosstools - mips crosstools - riscv
2013-11-01 17:40:39 +01:00
crosstools - i386 : clean - for - update
$ ( MAKE ) - C util / crossgcc build - i386
2015-03-13 22:50:22 +01:00
crosstools - x64 : clean - for - update
$ ( MAKE ) - C util / crossgcc build - x64
2013-11-01 17:40:39 +01:00
crosstools - arm : clean - for - update
$ ( MAKE ) - C util / crossgcc build - armv7a
2011-05-16 17:32:28 +02:00
2014-11-19 18:36:37 +01:00
crosstools - aarch64 : clean - for - update
$ ( MAKE ) - C util / crossgcc build - aarch64
2015-02-27 23:41:15 +01:00
crosstools - mips : clean - for - update
$ ( MAKE ) - C util / crossgcc build - mips
2015-03-07 10:57:25 +01:00
crosstools - riscv : clean - for - update
$ ( MAKE ) - C util / crossgcc build - riscv
2011-05-16 17:32:28 +02:00
crossgcc - clean : clean - for - update
$ ( MAKE ) - C util / crossgcc clean
2014-09-08 23:28:17 +02:00
tools : $ ( objutil ) / kconfig / conf $ ( objutil ) / cbfstool / cbfstool $ ( objutil ) / cbfstool / rmodtool $ ( objutil ) / nvramtool / nvramtool $ ( ROMCC_BIN ) $ ( objutil ) / sconfig / sconfig $ ( IFDTOOL ) $ ( IFDFAKE ) $ ( CBOOTIMAGE )
2011-11-05 14:44:41 +01:00
2014-04-23 01:33:22 +02:00
###########################################################################
# Common recipes for all stages
###########################################################################
New mechanism to define SRAM/memory map with automatic bounds checking
This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.
The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).
BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.
Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-08-21 00:29:56 +02:00
# loadaddr can determine the load address of a stage, which may be needed for
# platform-specific image headers (only works *after* the stage has been built)
loadaddr = $ ( shell $ ( OBJDUMP_ $ ( 1 )) - p $ ( objcbfs ) / $ ( 1 ) . debug | \
sed - ne '/LOAD/s/^.*vaddr 0x\([0-9a-fA-F]\{8\}\).*$$/0x\1/p' )
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
# find-substr is required for stages like romstage_null and romstage_xip to
# eliminate the _* part of the string
find - substr = $ ( word 1 , $ ( subst _ , , $ ( 1 )))
# find-class is used to identify the class from the name of the stage
# The input to this macro can be something like romstage.x or romstage.x.y
# find-class recursively strips off the suffixes to extract the exact class name
# e.g.: if romstage.x is provided to find-class, it will remove .x and return romstage
# if romstage.x.y is provided, it will first remove .y, call find-class with romstage.x
# and remove .x the next time and finally return romstage
find - class = $ ( if $ ( filter $ ( 1 ), $ ( basename $ ( 1 ))), $ ( if $ ( CC_ $ ( 1 )), $ ( 1 ), $ ( call find - substr , $ ( 1 ))), $ ( call find - class , $ ( basename $ ( 1 ))))
2014-04-23 01:33:22 +02:00
$ ( objcbfs ) /%. bin : $ ( objcbfs ) /%. elf
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
$ ( eval class : = $ ( call find - class , $ ( @ F )))
2014-04-23 01:33:22 +02:00
@ printf " OBJCOPY $ (subst $ (obj)/,, $ (@)) \n "
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
$ ( OBJCOPY_ $ ( class )) - O binary $ < $ @
2014-04-23 01:33:22 +02:00
$ ( objcbfs ) /%. elf : $ ( objcbfs ) /%. debug
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
$ ( eval class : = $ ( call find - class , $ ( @ F )))
2014-04-23 01:33:22 +02:00
@ printf " OBJCOPY $ (subst $ (obj)/,, $ (@)) \n "
cp $ < $ @. tmp
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
$ ( NM_ $ ( class )) - n $ @. tmp | sort > $ ( basename $ @ ) . map
$ ( OBJCOPY_ $ ( class )) -- strip - debug $ @. tmp
$ ( OBJCOPY_ $ ( class )) -- add - gnu - debuglink = $ < $ @. tmp
2014-04-23 01:33:22 +02:00
mv $ @. tmp $ @
###########################################################################
# Build the final rom image
###########################################################################
COREBOOT_ROM_DEPENDENCIES :=
ifeq ( $ ( CONFIG_PAYLOAD_ELF ), y )
COREBOOT_ROM_DEPENDENCIES += $ ( CONFIG_PAYLOAD_FILE )
endif
ifeq ( $ ( CONFIG_PAYLOAD_SEABIOS ), y )
COREBOOT_ROM_DEPENDENCIES += seabios
endif
ifeq ( $ ( CONFIG_PAYLOAD_FILO ), y )
COREBOOT_ROM_DEPENDENCIES += filo
endif
ifeq ( $ ( CONFIG_PAYLOAD_GRUB2 ), y )
COREBOOT_ROM_DEPENDENCIES += grub2
endif
2014-12-09 12:49:21 +01:00
extract_nth = $ ( patsubst -%- , % , $ ( word $ ( 1 ), $ ( subst | , - - , - $ ( 2 ) - )))
2014-04-23 01:33:22 +02:00
2014-12-09 12:49:21 +01:00
cbfs - add - cmd = \
2014-04-23 01:33:22 +02:00
$ ( CBFSTOOL ) $ @. tmp \
add $ ( if $ ( filter stage , $ ( call extract_nth , 3 , $ ( file ))), - stage ) $ ( if $ ( filter payload , $ ( call extract_nth , 3 , $ ( file ))), - payload ) \
- f $ ( call extract_nth , 1 , $ ( file )) \
2014-12-09 12:49:21 +01:00
- n $ ( call extract_nth , 2 , $ ( file )) $ ( if $ ( filter - out stage , $ ( call extract_nth , 3 , $ ( file ))), - t $ ( call extract_nth , 3 , $ ( file )))
ifneq ( $ ( CONFIG_UPDATE_IMAGE ), y )
prebuild - files = \
$ ( foreach file , $ ( cbfs - files ), \
$ ( if $ ( call extract_nth , 6 , $ ( file )), $ ( CBFSTOOL ) $ @. tmp locate - f $ ( call extract_nth , 1 , $ ( file )) - n $ ( call extract_nth , 2 , $ ( file )) - a $ ( call extract_nth , 6 , $ ( file )) | xargs - i \
$ ( cbfs - add - cmd ) - b {} && , \
$ ( cbfs - add - cmd ) $ ( if $ ( call extract_nth , 5 , $ ( file )), - b $ ( call extract_nth , 5 , $ ( file ))) && ))
2014-04-23 01:33:22 +02:00
prebuilt - files = $ ( foreach file , $ ( cbfs - files ), $ ( call extract_nth , 1 , $ ( file )))
$ ( obj ) / coreboot . pre1 : $ ( objcbfs ) / bootblock . bin $ $ ( prebuilt - files ) $ ( CBFSTOOL ) $ $ ( cpu_ucode_cbfs_file )
CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstool
Some projects (like ChromeOS) put more content than described by CBFS
onto their image. For top-aligned images (read: x86), this has
traditionally been achieved with a CBFS_SIZE Kconfig (which denotes the
area actually managed by CBFS, as opposed to ROM_SIZE) that is used to
calculate the CBFS entry start offset. On bottom-aligned boards, many
define a fake (smaller) ROM_SIZE for only the CBFS part, which is not
consistently done and can be an issue because ROM_SIZE is expected to be
a power of two.
This patch changes all non-x86 boards to describe their actual
(physical) ROM size via one of the BOARD_ROMSIZE_KB_xxx options as a
mainboard Kconfig select (which is the correct place to declare
unchangeable physical properties of the board). It also changes the
cbfstool create invocation to use CBFS_SIZE as the -s parameter for
those architectures, which defaults to ROM_SIZE but gets overridden for
special use cases like ChromeOS. This has the advantage that cbfstool
has a consistent idea of where the area it is responsible for ends,
which offers better bounds-checking and is needed for a subsequent fix.
Also change the FMAP offset to default to right behind the (now
consistently known) CBFS region for non-x86 boards, which has emerged as
a de-facto standard on those architectures and allows us to reduce the
amount of custom configuration. In the future, the nightmare that is
ChromeOS's image build system could be redesigned to enforce this
automatically, and also confirm that it doesn't overwrite any space used
by CBFS (which is now consistently defined as the file size of
coreboot.rom on non-x86).
CQ-DEPEND=CL:231576,CL:231475
BRANCH=None
BUG=chromium:422501
TEST=Built and booted on Veyron_Pinky.
Change-Id: I89aa5b30e25679e074d4cb5eee4c08178892ada6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e707c67c69599274b890d0686522880aa2e16d71
Original-Change-Id: I4fce5a56a8d72f4c4dd3a08c129025f1565351cc
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9619
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-10 22:11:50 +01:00
$ ( CBFSTOOL ) $ @. tmp create \
2014-04-23 01:33:22 +02:00
- B $ ( objcbfs ) / bootblock . bin - a 64 \
$ ( CBFSTOOL_PRE1_OPTS )
$ ( prebuild - files ) true
$ ( call add - cpu - microcode - to - cbfs , $ @. tmp )
mv $ @. tmp $ @
else
. PHONY : $ ( obj ) / coreboot . pre1
$ ( obj ) / coreboot . pre1 : $ ( CBFSTOOL )
mv $ ( obj ) / coreboot . rom $ @
endif
ifeq ( $ ( CONFIG_PAYLOAD_LINUX ), y )
ifneq ( $ ( strip $ ( call strip_quotes , $ ( CONFIG_LINUX_COMMAND_LINE ))),)
2014-05-17 14:11:57 +02:00
ADDITIONAL_PAYLOAD_CONFIG +=- C $ ( CONFIG_LINUX_COMMAND_LINE )
2014-04-23 01:33:22 +02:00
endif
ifneq ( $ ( strip $ ( call strip_quotes , $ ( CONFIG_LINUX_INITRD ))),)
2014-05-17 14:11:57 +02:00
ADDITIONAL_PAYLOAD_CONFIG +=- I $ ( CONFIG_LINUX_INITRD )
2014-04-23 01:33:22 +02:00
endif
endif
ifeq ( $ ( CONFIG_HAVE_REFCODE_BLOB ), y )
REFCODE_BLOB = $ ( obj ) / refcode . rmod
$ ( REFCODE_BLOB ) : $ ( RMODTOOL )
$ ( RMODTOOL ) - i $ ( CONFIG_REFCODE_BLOB_FILE ) - o $ @
endif
$ ( obj ) / coreboot . rom : $ ( obj ) / coreboot . pre $ ( objcbfs ) / ramstage . elf $ ( CBFSTOOL ) $ ( call strip_quotes , $ ( COREBOOT_ROM_DEPENDENCIES )) $ $ ( INTERMEDIATE ) $ $ ( VBOOT_STUB ) $ ( REFCODE_BLOB )
@ printf " CBFS $ (subst $ (obj)/,, $ (@)) \n "
CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstool
Some projects (like ChromeOS) put more content than described by CBFS
onto their image. For top-aligned images (read: x86), this has
traditionally been achieved with a CBFS_SIZE Kconfig (which denotes the
area actually managed by CBFS, as opposed to ROM_SIZE) that is used to
calculate the CBFS entry start offset. On bottom-aligned boards, many
define a fake (smaller) ROM_SIZE for only the CBFS part, which is not
consistently done and can be an issue because ROM_SIZE is expected to be
a power of two.
This patch changes all non-x86 boards to describe their actual
(physical) ROM size via one of the BOARD_ROMSIZE_KB_xxx options as a
mainboard Kconfig select (which is the correct place to declare
unchangeable physical properties of the board). It also changes the
cbfstool create invocation to use CBFS_SIZE as the -s parameter for
those architectures, which defaults to ROM_SIZE but gets overridden for
special use cases like ChromeOS. This has the advantage that cbfstool
has a consistent idea of where the area it is responsible for ends,
which offers better bounds-checking and is needed for a subsequent fix.
Also change the FMAP offset to default to right behind the (now
consistently known) CBFS region for non-x86 boards, which has emerged as
a de-facto standard on those architectures and allows us to reduce the
amount of custom configuration. In the future, the nightmare that is
ChromeOS's image build system could be redesigned to enforce this
automatically, and also confirm that it doesn't overwrite any space used
by CBFS (which is now consistently defined as the file size of
coreboot.rom on non-x86).
CQ-DEPEND=CL:231576,CL:231475
BRANCH=None
BUG=chromium:422501
TEST=Built and booted on Veyron_Pinky.
Change-Id: I89aa5b30e25679e074d4cb5eee4c08178892ada6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e707c67c69599274b890d0686522880aa2e16d71
Original-Change-Id: I4fce5a56a8d72f4c4dd3a08c129025f1565351cc
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9619
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-10 22:11:50 +01:00
# The full ROM may be larger than the CBFS part, so create an empty
# file (filled with \377 = 0xff) and copy the CBFS image over it.
2015-04-17 14:32:34 +02:00
dd if =/ dev / zero bs = $ ( CONFIG_ROM_SIZE ) count = 1 | tr '\000' '\377' > $ @. tmp
CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstool
Some projects (like ChromeOS) put more content than described by CBFS
onto their image. For top-aligned images (read: x86), this has
traditionally been achieved with a CBFS_SIZE Kconfig (which denotes the
area actually managed by CBFS, as opposed to ROM_SIZE) that is used to
calculate the CBFS entry start offset. On bottom-aligned boards, many
define a fake (smaller) ROM_SIZE for only the CBFS part, which is not
consistently done and can be an issue because ROM_SIZE is expected to be
a power of two.
This patch changes all non-x86 boards to describe their actual
(physical) ROM size via one of the BOARD_ROMSIZE_KB_xxx options as a
mainboard Kconfig select (which is the correct place to declare
unchangeable physical properties of the board). It also changes the
cbfstool create invocation to use CBFS_SIZE as the -s parameter for
those architectures, which defaults to ROM_SIZE but gets overridden for
special use cases like ChromeOS. This has the advantage that cbfstool
has a consistent idea of where the area it is responsible for ends,
which offers better bounds-checking and is needed for a subsequent fix.
Also change the FMAP offset to default to right behind the (now
consistently known) CBFS region for non-x86 boards, which has emerged as
a de-facto standard on those architectures and allows us to reduce the
amount of custom configuration. In the future, the nightmare that is
ChromeOS's image build system could be redesigned to enforce this
automatically, and also confirm that it doesn't overwrite any space used
by CBFS (which is now consistently defined as the file size of
coreboot.rom on non-x86).
CQ-DEPEND=CL:231576,CL:231475
BRANCH=None
BUG=chromium:422501
TEST=Built and booted on Veyron_Pinky.
Change-Id: I89aa5b30e25679e074d4cb5eee4c08178892ada6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e707c67c69599274b890d0686522880aa2e16d71
Original-Change-Id: I4fce5a56a8d72f4c4dd3a08c129025f1565351cc
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229974
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9619
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-10 22:11:50 +01:00
dd if = $ ( obj ) / coreboot . pre of = $ @. tmp bs = 8192 conv = notrunc 2 > / dev / null
2014-04-23 01:33:22 +02:00
$ ( CBFSTOOL ) $ @. tmp add - stage - f $ ( objcbfs ) / ramstage . elf - n $ ( CONFIG_CBFS_PREFIX ) / ramstage - c $ ( CBFS_COMPRESS_FLAG )
ifeq ( $ ( CONFIG_PAYLOAD_NONE ), y )
@ printf " PAYLOAD none (as specified by user) \n "
endif
2014-05-17 14:11:57 +02:00
ifneq ( $ ( CONFIG_PAYLOAD_FILE ),)
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@ printf " PAYLOAD $ (CONFIG_PAYLOAD_FILE) (compression: $ (CBFS_PAYLOAD_COMPRESS_FLAG)) \n "
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$ ( CBFSTOOL ) $ @. tmp add - payload - f $ ( CONFIG_PAYLOAD_FILE ) - n $ ( CONFIG_CBFS_PREFIX ) / payload - c $ ( CBFS_PAYLOAD_COMPRESS_FLAG ) $ ( ADDITIONAL_PAYLOAD_CONFIG )
2014-04-23 01:33:22 +02:00
endif
ifneq ( $ ( CONFIG_SEABIOS_PS2_TIMEOUT ),)
ifneq ( $ ( CONFIG_SEABIOS_PS2_TIMEOUT ), 0 )
@ printf " SeaBIOS Wait up to $ (CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization \n "
$ ( CBFSTOOL ) $ @. tmp add - int - i $ ( CONFIG_SEABIOS_PS2_TIMEOUT ) - n etc / ps2 - keyboard - spinup
endif
endif
2014-09-12 19:43:49 +02:00
ifeq ( $ ( CONFIG_SEABIOS_VGA_COREBOOT ), y )
@ printf " SeaBIOS Adding generated legacy VGA option rom. \n "
$ ( CBFSTOOL ) $ @. tmp add - f $ ( CONFIG_PAYLOAD_VGABIOS_FILE ) - n vgaroms / seavgabios . bin - t raw
endif
2014-04-23 01:33:22 +02:00
ifeq ( $ ( CONFIG_INCLUDE_CONFIG_FILE ), y )
@ printf " CONFIG $ (DOTCONFIG) \n "
if [ - f $ ( DOTCONFIG ) ]; then \
echo " # This image was built using git revision " `git rev-parse HEAD` > $ ( obj ) / config . tmp ; \
sed - e '/^#/d' - e '/^ *$$/d' $ ( DOTCONFIG ) >> $ ( obj ) / config . tmp ; \
$ ( CBFSTOOL ) $ @. tmp add - f $ ( obj ) / config . tmp - n config - t raw ; rm - f $ ( obj ) / config . tmp ; fi
2014-08-23 01:08:09 +02:00
@ printf " REVISION build.h \n "
if [ - f $ ( obj ) / build . h ]; then $ ( CBFSTOOL ) $ @. tmp add - f $ ( obj ) / build . h - n revision - t raw ; fi
2014-04-23 01:33:22 +02:00
endif
ifeq ( $ ( CONFIG_VBOOT_VERIFY_FIRMWARE ), y )
$ ( CBFSTOOL ) $ @. tmp add - stage - f $ ( VBOOT_STUB ) - n $ ( CONFIG_CBFS_PREFIX ) / vboot - c $ ( CBFS_COMPRESS_FLAG )
endif
ifeq ( $ ( CONFIG_HAVE_REFCODE_BLOB ), y )
$ ( CBFSTOOL ) $ @. tmp add - stage - f $ ( REFCODE_BLOB ) - n $ ( CONFIG_CBFS_PREFIX ) / refcode - c $ ( CBFS_COMPRESS_FLAG )
endif
ifeq ( $ ( CONFIG_PXE_ROM ), y )
$ ( CBFSTOOL ) $ @. tmp add - f $ ( CONFIG_PXE_ROM_FILE ) - n pci $ ( CONFIG_PXE_ROM_ID ) . rom - t raw
endif
ifeq ( $ ( CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE ), y )
2014-12-27 10:55:47 +01:00
ifeq ( $ ( CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD ), y )
2014-04-23 01:33:22 +02:00
@ printf " UPDATE-FIT \n "
$ ( CBFSTOOL ) $ @. tmp update - fit - n cpu_microcode_blob . bin - x $ ( CONFIG_CPU_INTEL_NUM_FIT_ENTRIES )
endif
endif
mv $ @. tmp $ @
@ printf " CBFSPRINT $ (subst $ (obj)/,, $ (@)) \n \n "
$ ( CBFSTOOL ) $ @ print
cbfs - files - $ ( CONFIG_BOOTSPLASH ) += bootsplash . jpg
bootsplash . jpg - file := $ ( call strip_quotes , $ ( CONFIG_BOOTSPLASH_FILE ))
bootsplash . jpg - type := bootsplash
2014-11-29 11:51:25 +01:00
$ ( obj ) / coreboot . pre : $ ( objcbfs ) / romstage . elf $ ( obj ) / coreboot . pre1 $ ( CBFSTOOL )
2014-04-23 01:33:22 +02:00
@ printf " CBFS $ (subst $ (obj)/,, $ (@)) \n "
cp $ ( obj ) / coreboot . pre1 $ @. tmp
$ ( CBFSTOOL ) $ @. tmp add - stage \
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- f $ ( objcbfs ) / romstage . elf \
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- n $ ( CONFIG_CBFS_PREFIX ) / romstage - c none \
$ ( CBFSTOOL_PRE_OPTS )
mv $ @. tmp $ @
2014-08-29 20:10:38 +02:00
2015-03-27 00:29:00 +01:00
cbfs - files - $ ( CONFIG_BOARD_ID_MANUAL ) += board_id
board_id - file := $ ( obj ) / board_id
board_id - type := raw
$ ( obj ) / board_id :
printf " $ (CONFIG_BOARD_ID_STRING) " > $ @
2014-08-29 20:10:38 +02:00
JENKINS_PAYLOAD = none
what - jenkins - does :
2015-02-17 12:21:32 +01:00
util / abuild / abuild - B - J $ ( if $ ( JENKINS_NOCCACHE ),, - y ) - c 4 - z - p $ ( JENKINS_PAYLOAD )
( cd payloads / libpayload ; $ ( MAKE ) $ ( if $ ( JENKINS_NOCCACHE ),, CONFIG_CCACHE = y ) V = $ ( V ) Q = $ ( Q ) junit . xml )
2014-08-29 20:10:38 +02:00
$ ( MAKE ) V = $ ( V ) Q = $ ( Q ) - C util / cbmem junit . xml
