2015-03-15 04:29:35 +01:00
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009-2010 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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2015-04-04 01:58:28 +02:00
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config ARCH_X86
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bool
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default n
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select PCI
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Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
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config ARCH_BOOTBLOCK_X86_32
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2013-07-07 22:52:37 +02:00
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bool
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Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
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default n
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select ARCH_X86
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2015-01-14 19:51:47 +01:00
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config ARCH_VERSTAGE_X86_32
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bool
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default n
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Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
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config ARCH_ROMSTAGE_X86_32
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bool
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default n
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config ARCH_RAMSTAGE_X86_32
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bool
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default n
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2013-07-07 22:52:37 +02:00
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2009-10-07 18:15:40 +02:00
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# This is an SMP option. It relates to starting up APs.
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# It is usually set in mainboard/*/Kconfig.
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# TODO: Improve description.
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2012-07-29 19:18:03 +02:00
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config AP_IN_SIPI_WAIT
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bool
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default n
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2012-10-15 22:38:09 +02:00
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depends on ARCH_X86 && SMP
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2009-08-29 04:59:35 +02:00
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2012-04-06 03:03:50 +02:00
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# Aligns 16bit entry code in bootblock so that hyper-threading CPUs
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# can boot AP CPUs to enable their shared caches.
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config SIPI_VECTOR_IN_ROM
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bool
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default n
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depends on ARCH_X86
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2009-08-12 17:00:51 +02:00
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config RAMBASE
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hex
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default 0x100000
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2013-07-22 20:17:18 +02:00
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# This is something you almost certainly don't want to mess with.
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# How many SIPIs do we send when starting up APs and cores?
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# The answer in 2000 or so was '2'. Nowadays, on many systems,
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# it is 1. Set a safe default here, and you can override it
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# on reasonable platforms.
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config NUM_IPI_STARTS
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int
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default 2
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2010-02-09 13:21:10 +01:00
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config ROMCC
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bool
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default n
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2014-12-31 19:55:19 +01:00
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config LATE_CBMEM_INIT
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def_bool n
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help
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Enable this in chipset's Kconfig if northbridge does not implement
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early get_top_of_ram() call for romstage. CBMEM tables will be
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allocated late in ramstage, after PCI devices resources are known.
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2010-12-17 00:37:17 +01:00
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config PC80_SYSTEM
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bool
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Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
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default y if ARCH_X86
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2010-12-17 00:37:17 +01:00
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2012-11-14 07:08:50 +01:00
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config BOOTBLOCK_MAINBOARD_INIT
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string
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2009-12-31 13:56:53 +01:00
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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2011-01-14 08:40:24 +01:00
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config HAVE_CMOS_DEFAULT
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def_bool n
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config CMOS_DEFAULT_FILE
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string
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2013-05-28 13:46:12 +02:00
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default "src/mainboard/$(MAINBOARDDIR)/cmos.default"
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2011-01-14 08:40:24 +01:00
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depends on HAVE_CMOS_DEFAULT
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2009-12-31 13:56:53 +01:00
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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2011-01-05 03:27:53 +01:00
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2012-03-16 19:28:15 +01:00
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config IOAPIC_INTERRUPTS_ON_FSB
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bool
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default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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bool
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default n
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2012-10-05 21:54:38 +02:00
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config HPET_ADDRESS
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hex
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default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
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2012-11-14 00:04:12 +01:00
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config ID_SECTION_OFFSET
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hex
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default 0x80
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