2020-04-02 23:48:16 +02:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
#include <console/console.h>
|
|
|
|
#include <device/device.h>
|
|
|
|
#include <device/pci.h>
|
|
|
|
#include <device/azalia_device.h>
|
2019-03-03 07:01:05 +01:00
|
|
|
#include <device/mmio.h>
|
2013-08-12 14:07:47 +02:00
|
|
|
#include <delay.h>
|
2021-02-16 09:18:07 +01:00
|
|
|
#include <timer.h>
|
2013-08-12 14:07:47 +02:00
|
|
|
|
2020-12-05 18:02:32 +01:00
|
|
|
int azalia_set_bits(void *port, u32 mask, u32 val)
|
2013-08-12 14:07:47 +02:00
|
|
|
{
|
2021-02-16 09:18:07 +01:00
|
|
|
struct stopwatch sw;
|
2013-08-12 14:07:47 +02:00
|
|
|
u32 reg32;
|
|
|
|
|
|
|
|
/* Write (val & mask) to port */
|
|
|
|
val &= mask;
|
|
|
|
reg32 = read32(port);
|
|
|
|
reg32 &= ~mask;
|
|
|
|
reg32 |= val;
|
|
|
|
write32(port, reg32);
|
|
|
|
|
2020-08-11 09:21:24 +02:00
|
|
|
/* Wait for readback of register to match what was just written to it */
|
2021-02-16 09:18:07 +01:00
|
|
|
stopwatch_init_msecs_expire(&sw, 50);
|
2013-08-12 14:07:47 +02:00
|
|
|
do {
|
|
|
|
/* Wait 1ms based on BKDG wait time */
|
|
|
|
mdelay(1);
|
|
|
|
reg32 = read32(port);
|
|
|
|
reg32 &= mask;
|
2021-02-16 09:18:07 +01:00
|
|
|
} while ((reg32 != val) && !stopwatch_expired(&sw));
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
/* Timeout occurred */
|
2021-02-16 09:18:07 +01:00
|
|
|
if (stopwatch_expired(&sw))
|
2013-08-12 14:07:47 +02:00
|
|
|
return -1;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-12-05 18:52:38 +01:00
|
|
|
int azalia_enter_reset(u8 *base)
|
|
|
|
{
|
|
|
|
/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
|
|
|
|
return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
int azalia_exit_reset(u8 *base)
|
|
|
|
{
|
|
|
|
/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
|
|
|
|
return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST);
|
|
|
|
}
|
|
|
|
|
2021-03-18 15:43:42 +01:00
|
|
|
static u16 codec_detect(u8 *base)
|
2013-08-12 14:07:47 +02:00
|
|
|
{
|
2021-02-16 09:18:07 +01:00
|
|
|
struct stopwatch sw;
|
2021-03-18 16:00:14 +01:00
|
|
|
const u16 codec_mask = (1 << CONFIG_AZALIA_MAX_CODECS) - 1;
|
2021-03-18 15:43:42 +01:00
|
|
|
u16 reg16;
|
2013-08-12 14:07:47 +02:00
|
|
|
|
2020-12-05 19:02:14 +01:00
|
|
|
if (azalia_exit_reset(base) < 0)
|
2013-08-12 14:07:47 +02:00
|
|
|
goto no_codec;
|
|
|
|
|
2021-03-22 14:21:28 +01:00
|
|
|
if (CONFIG(AZALIA_LOCK_DOWN_R_WO_GCAP)) {
|
|
|
|
/* If GCAP is R/WO, lock it down after deasserting controller reset */
|
|
|
|
write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
|
|
|
|
}
|
|
|
|
|
2020-08-11 09:21:24 +02:00
|
|
|
/* clear STATESTS bits (BAR + 0xe)[2:0] */
|
2021-03-18 15:43:42 +01:00
|
|
|
reg16 = read16(base + HDA_STATESTS_REG);
|
2021-03-18 16:00:14 +01:00
|
|
|
reg16 |= codec_mask;
|
2021-03-18 15:43:42 +01:00
|
|
|
write16(base + HDA_STATESTS_REG, reg16);
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
/* Wait for readback of register to
|
|
|
|
* match what was just written to it
|
|
|
|
*/
|
2021-02-16 09:18:07 +01:00
|
|
|
stopwatch_init_msecs_expire(&sw, 50);
|
2013-08-12 14:07:47 +02:00
|
|
|
do {
|
|
|
|
/* Wait 1ms based on BKDG wait time */
|
|
|
|
mdelay(1);
|
2021-03-18 15:43:42 +01:00
|
|
|
reg16 = read16(base + HDA_STATESTS_REG);
|
|
|
|
} while ((reg16 != 0) && !stopwatch_expired(&sw));
|
2021-02-16 09:18:07 +01:00
|
|
|
|
2016-01-06 04:58:58 +01:00
|
|
|
/* Timeout occurred */
|
2021-02-16 09:18:07 +01:00
|
|
|
if (stopwatch_expired(&sw))
|
2013-08-12 14:07:47 +02:00
|
|
|
goto no_codec;
|
|
|
|
|
2020-12-05 19:06:55 +01:00
|
|
|
if (azalia_enter_reset(base) < 0)
|
2013-08-12 14:07:47 +02:00
|
|
|
goto no_codec;
|
|
|
|
|
2020-12-05 19:02:14 +01:00
|
|
|
if (azalia_exit_reset(base) < 0)
|
2013-08-12 14:07:47 +02:00
|
|
|
goto no_codec;
|
|
|
|
|
|
|
|
/* Read in Codec location (BAR + 0xe)[2..0] */
|
2021-03-18 15:43:42 +01:00
|
|
|
reg16 = read16(base + HDA_STATESTS_REG);
|
2021-03-18 16:00:14 +01:00
|
|
|
reg16 &= codec_mask;
|
2021-03-18 15:43:42 +01:00
|
|
|
if (!reg16)
|
2013-08-12 14:07:47 +02:00
|
|
|
goto no_codec;
|
|
|
|
|
2021-03-18 15:43:42 +01:00
|
|
|
return reg16;
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
no_codec:
|
|
|
|
/* Codec Not found */
|
|
|
|
/* Put HDA back in reset (BAR + 0x8) [0] */
|
2020-12-05 18:02:32 +01:00
|
|
|
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
|
2013-08-12 14:07:47 +02:00
|
|
|
printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-12-05 18:28:33 +01:00
|
|
|
/*
|
|
|
|
* Find a specific entry within a verb table
|
|
|
|
*
|
|
|
|
* @param verb_table: verb table data
|
|
|
|
* @param verb_table_bytes: verb table size in bytes
|
|
|
|
* @param viddid: vendor/device to search for
|
|
|
|
* @param verb: pointer to entry within table
|
|
|
|
*
|
|
|
|
* Returns size of the entry within the verb table,
|
|
|
|
* Returns 0 if the entry is not found
|
|
|
|
*
|
|
|
|
* The HDA verb table is composed of dwords. A set of 4 dwords is
|
|
|
|
* grouped together to form a "jack" descriptor.
|
|
|
|
* Bits 31:28 - Codec Address
|
|
|
|
* Bits 27:20 - NID
|
|
|
|
* Bits 19:8 - Verb ID
|
|
|
|
* Bits 7:0 - Payload
|
|
|
|
*
|
|
|
|
* coreboot groups different codec verb tables into a single table
|
|
|
|
* and prefixes each with a specific header consisting of 3
|
|
|
|
* dword entries:
|
|
|
|
* 1 - Codec Vendor/Device ID
|
|
|
|
* 2 - Subsystem ID
|
|
|
|
* 3 - Number of jacks (groups of 4 dwords) for this codec
|
|
|
|
*/
|
2020-12-05 18:22:58 +01:00
|
|
|
u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb)
|
2013-08-12 14:07:47 +02:00
|
|
|
{
|
|
|
|
int idx = 0;
|
|
|
|
|
2020-12-05 18:22:58 +01:00
|
|
|
while (idx < (verb_table_bytes / sizeof(u32))) {
|
2020-12-05 18:32:05 +01:00
|
|
|
/* Header contains the number of jacks, aka groups of 4 dwords */
|
|
|
|
u32 verb_size = 4 * verb_table[idx + 2];
|
2020-12-05 18:22:58 +01:00
|
|
|
if (verb_table[idx] != viddid) {
|
2013-08-12 14:07:47 +02:00
|
|
|
idx += verb_size + 3; // skip verb + header
|
|
|
|
continue;
|
|
|
|
}
|
2020-12-05 18:22:58 +01:00
|
|
|
*verb = &verb_table[idx + 3];
|
2013-08-12 14:07:47 +02:00
|
|
|
return verb_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Not all codecs need to load another verb */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-08-11 09:21:24 +02:00
|
|
|
/*
|
|
|
|
* Wait 50usec for the codec to indicate it is ready.
|
|
|
|
* No response would imply that the codec is non-operative.
|
2013-08-12 14:07:47 +02:00
|
|
|
*/
|
|
|
|
|
2014-12-25 03:43:20 +01:00
|
|
|
static int wait_for_ready(u8 *base)
|
2013-08-12 14:07:47 +02:00
|
|
|
{
|
2021-02-16 09:18:07 +01:00
|
|
|
struct stopwatch sw;
|
2020-08-11 09:21:24 +02:00
|
|
|
/* Use a 50 usec timeout - the Linux kernel uses the same duration */
|
2021-02-16 09:18:07 +01:00
|
|
|
stopwatch_init_usecs_expire(&sw, 50);
|
2013-08-12 14:07:47 +02:00
|
|
|
|
2021-02-16 09:18:07 +01:00
|
|
|
while (!stopwatch_expired(&sw)) {
|
2013-08-12 14:07:47 +02:00
|
|
|
u32 reg32 = read32(base + HDA_ICII_REG);
|
|
|
|
if (!(reg32 & HDA_ICII_BUSY))
|
|
|
|
return 0;
|
|
|
|
udelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2020-08-11 09:21:24 +02:00
|
|
|
/*
|
2021-03-18 14:12:32 +01:00
|
|
|
* Wait for the codec to indicate that it accepted the previous command.
|
|
|
|
* No response would imply that the codec is non-operative.
|
2013-08-12 14:07:47 +02:00
|
|
|
*/
|
|
|
|
|
2014-12-25 03:43:20 +01:00
|
|
|
static int wait_for_valid(u8 *base)
|
2013-08-12 14:07:47 +02:00
|
|
|
{
|
2021-02-16 09:18:07 +01:00
|
|
|
struct stopwatch sw;
|
2020-08-11 09:21:24 +02:00
|
|
|
u32 reg32;
|
2013-08-12 14:07:47 +02:00
|
|
|
|
2020-08-11 09:21:24 +02:00
|
|
|
/* Send the verb to the codec */
|
|
|
|
reg32 = read32(base + HDA_ICII_REG);
|
|
|
|
reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
|
|
|
|
write32(base + HDA_ICII_REG, reg32);
|
|
|
|
|
2021-03-18 14:12:32 +01:00
|
|
|
/*
|
|
|
|
* The timeout is never reached when the codec is functioning properly.
|
|
|
|
* Using a small timeout value can result in spurious errors with some
|
|
|
|
* codecs, e.g. a codec that is slow to respond but operates correctly.
|
|
|
|
* When a codec is non-operative, the timeout is only reached once per
|
|
|
|
* verb table, thus the impact on booting time is relatively small. So,
|
|
|
|
* use a reasonably long enough timeout to cover all possible cases.
|
|
|
|
*/
|
|
|
|
stopwatch_init_msecs_expire(&sw, 1);
|
2021-02-16 09:18:07 +01:00
|
|
|
while (!stopwatch_expired(&sw)) {
|
2020-08-11 09:21:24 +02:00
|
|
|
reg32 = read32(base + HDA_ICII_REG);
|
|
|
|
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID)
|
2013-08-12 14:07:47 +02:00
|
|
|
return 0;
|
|
|
|
udelay(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2021-02-08 12:37:56 +01:00
|
|
|
static int azalia_write_verb(u8 *base, u32 verb)
|
|
|
|
{
|
|
|
|
if (wait_for_ready(base) < 0)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
write32(base + HDA_IC_REG, verb);
|
|
|
|
|
|
|
|
return wait_for_valid(base);
|
|
|
|
}
|
|
|
|
|
|
|
|
int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size)
|
|
|
|
{
|
|
|
|
if (!verbs)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (u32 i = 0; i < verb_size; i++) {
|
|
|
|
if (azalia_write_verb(base, verbs[i]) < 0)
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-02-08 12:47:29 +01:00
|
|
|
__weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2014-12-25 03:43:20 +01:00
|
|
|
static void codec_init(struct device *dev, u8 *base, int addr)
|
2013-08-12 14:07:47 +02:00
|
|
|
{
|
|
|
|
u32 reg32;
|
|
|
|
const u32 *verb;
|
|
|
|
u32 verb_size;
|
|
|
|
|
|
|
|
printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr);
|
|
|
|
|
|
|
|
/* 1 */
|
2020-10-24 23:23:07 +02:00
|
|
|
if (wait_for_ready(base) < 0) {
|
2020-08-11 09:21:24 +02:00
|
|
|
printk(BIOS_DEBUG, " codec not ready.\n");
|
2013-08-12 14:07:47 +02:00
|
|
|
return;
|
2020-08-11 09:21:24 +02:00
|
|
|
}
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
reg32 = (addr << 28) | 0x000f0000;
|
2020-08-03 15:31:39 +02:00
|
|
|
write32(base + HDA_IC_REG, reg32);
|
2013-08-12 14:07:47 +02:00
|
|
|
|
2020-10-24 23:23:07 +02:00
|
|
|
if (wait_for_valid(base) < 0) {
|
2020-08-11 09:21:24 +02:00
|
|
|
printk(BIOS_DEBUG, " codec not valid.\n");
|
2013-08-12 14:07:47 +02:00
|
|
|
return;
|
2020-08-11 09:21:24 +02:00
|
|
|
}
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
/* 2 */
|
2020-08-11 09:21:24 +02:00
|
|
|
reg32 = read32(base + HDA_IR_REG);
|
2013-08-12 14:07:47 +02:00
|
|
|
printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
|
2020-12-05 18:22:58 +01:00
|
|
|
verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
if (!verb_size) {
|
|
|
|
printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
|
|
|
|
return;
|
|
|
|
}
|
2021-02-08 12:40:06 +01:00
|
|
|
printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size);
|
2013-08-12 14:07:47 +02:00
|
|
|
|
|
|
|
/* 3 */
|
2021-02-08 12:37:56 +01:00
|
|
|
azalia_program_verb_table(base, verb, verb_size);
|
2013-08-12 14:07:47 +02:00
|
|
|
printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
|
2021-02-08 12:47:29 +01:00
|
|
|
|
|
|
|
mainboard_azalia_program_runtime_verbs(base, reg32);
|
2013-08-12 14:07:47 +02:00
|
|
|
}
|
|
|
|
|
2021-03-18 15:43:42 +01:00
|
|
|
static void codecs_init(struct device *dev, u8 *base, u16 codec_mask)
|
2013-08-12 14:07:47 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2021-03-18 16:00:14 +01:00
|
|
|
for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
|
2013-08-12 14:07:47 +02:00
|
|
|
if (codec_mask & (1 << i))
|
|
|
|
codec_init(dev, base, i);
|
|
|
|
}
|
2021-02-16 10:03:07 +01:00
|
|
|
|
|
|
|
azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
|
2013-08-12 14:07:47 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void azalia_audio_init(struct device *dev)
|
|
|
|
{
|
2014-12-25 03:43:20 +01:00
|
|
|
u8 *base;
|
2013-08-12 14:07:47 +02:00
|
|
|
struct resource *res;
|
2021-03-18 15:43:42 +01:00
|
|
|
u16 codec_mask;
|
2013-08-12 14:07:47 +02:00
|
|
|
|
2020-08-11 09:21:24 +02:00
|
|
|
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
2013-08-12 14:07:47 +02:00
|
|
|
if (!res)
|
|
|
|
return;
|
|
|
|
|
2021-10-01 22:28:22 +02:00
|
|
|
// NOTE this will break as soon as the azalia_audio gets a bar above 4G.
|
2020-08-11 09:21:24 +02:00
|
|
|
// Is there anything we can do about it?
|
2014-12-25 03:43:20 +01:00
|
|
|
base = res2mmio(res, 0, 0);
|
|
|
|
printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
|
2013-08-12 14:07:47 +02:00
|
|
|
codec_mask = codec_detect(base);
|
|
|
|
|
|
|
|
if (codec_mask) {
|
2020-08-11 09:21:24 +02:00
|
|
|
printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask);
|
2013-08-12 14:07:47 +02:00
|
|
|
codecs_init(dev, base, codec_mask);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
struct device_operations default_azalia_audio_ops = {
|
|
|
|
.read_resources = pci_dev_read_resources,
|
|
|
|
.set_resources = pci_dev_set_resources,
|
|
|
|
.enable_resources = pci_dev_enable_resources,
|
|
|
|
.init = azalia_audio_init,
|
2020-05-31 00:03:28 +02:00
|
|
|
.ops_pci = &pci_dev_ops_pci,
|
2013-08-12 14:07:47 +02:00
|
|
|
};
|