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coreboot-kgpe-d16/src/soc/intel/apollolake/graphics.c

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soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:06:15 +01:00
/*
* This file is part of the coreboot project.
*
soc/intel/apollolake: Make use of Intel common Graphics block TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 13:24:15 +01:00
* Copyright (C) 2015-2017 Intel Corp.
soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:06:15 +01:00
* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
#include <arch/acpigen.h>
soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:06:15 +01:00
#include <console/console.h>
#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
soc/intel/apollolake: Make use of Intel common Graphics block TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 13:24:15 +01:00
#include <intelblocks/graphics.h>
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
#include <soc/intel/common/opregion.h>
soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:06:15 +01:00
driver/intel/fsp20: move lb_framebuffer function move lb_framebuffer function in soc/intel/apollolake to driver/intel/fsp20 so that fsp 2.0 bases soc's can use common lb_framebuffer function. Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-08 18:57:04 +02:00
uintptr_t fsp_soc_get_igd_bar(void)
soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:06:15 +01:00
{
soc/intel/apollolake: Make use of Intel common Graphics block TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 13:24:15 +01:00
return graphics_get_memory_base();
soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ia8311da9b9a603ea9b333ea873fc26d11e182332 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14764 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-12-16 01:06:15 +01:00
}
soc/intel/apollolake: Make use of Intel common Graphics block TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 13:24:15 +01:00
uintptr_t graphics_soc_write_acpi_opregion(struct device *device,
uintptr_t current, struct acpi_rsdp *rsdp)
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
{
igd_opregion_t *opregion;
uint16_t reg16;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
soc/intel/common/opregion: Use enum cb_err as return value Return CB_SUCCESS and CB_ERR instead of some integer. Preparation to merge intel/soc and intel/nb opregion implementations. Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 08:43:11 +02:00
if (init_igd_opregion(opregion) != CB_SUCCESS)
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
return current;
current += sizeof(igd_opregion_t);
/* TODO Initialize Mailbox 3 */
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
/*
* TODO This needs to happen in S3 resume, too.
* Maybe it should move to the finalize handler.
*/
soc/intel/apollolake: Make use of Intel common Graphics block TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 13:24:15 +01:00
pci_write_config32(device, ASLS, (uintptr_t)opregion);
reg16 = pci_read_config16(device, SWSCI);
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
reg16 &= ~(1 << 0);
reg16 |= (1 << 15);
soc/intel/apollolake: Make use of Intel common Graphics block TEST=Build and boot reef. Change-Id: I0edd7454912201598c43e35990e470ec18a32638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 13:24:15 +01:00
pci_write_config16(device, SWSCI, reg16);
soc/intel/apollolake: Take advantage of common opregion code Change-Id: I2d16336513bcd5a0544a6b68b609e40dd7c141fb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14807 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-13 04:11:48 +02:00
return acpi_align_current(current);
}
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