37 lines
866 B
C
37 lines
866 B
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor PCH Datasheet
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* Document number: 621483
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* Chapter number: 3
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*/
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#include <console/console.h>
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#include <intelblocks/p2sb.h>
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void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
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{
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uint32_t mask;
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if (count != P2SB_EP_MASK_MAX_REG) {
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printk(BIOS_ERR, "Unable to program EPMASK registers\n");
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return;
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}
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/* Remove the host accessing right to PSF register range.
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* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband
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* access for PCI Root Bridge.
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*/
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mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
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ep_mask[P2SB_EP_MASK_5_REG] = mask;
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/*
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* Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband
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* access for Broadcast and Multicast.
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*/
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mask = (1 << 31) | (1 << 30);
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ep_mask[P2SB_EP_MASK_7_REG] = mask;
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}
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