Subrata Banik e633804375 soc/intel/alderlake: Use devfn_disable() function for XDCI ... Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I5e10e5d0b80986e1e73573a86a957985840fe0b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55727 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-23 08:26:27 +00:00
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acpi	soc/intel/alderlake: Update ACPI device ID of IOM	2021-06-07 17:40:17 +00:00
bootblock	soc/intel/alderlake: Add GFx Device ID 0x46b3	2021-06-21 05:38:58 +00:00
include/soc	soc/intel/{alderlake,tigerlake}: Fix typo in pmc.h	2021-06-17 15:59:29 +00:00
romstage	soc/intel/alderlake/romstage: Refactor soc_memory_init_params function	2021-06-17 05:43:11 +00:00
spd	soc/intel/alderlake: Add new memory parts for ADL boards	2021-06-03 15:51:17 +00:00
acpi.c	soc/intel/alderlake: Make use of is_devfn_enabled() function	2021-06-16 03:49:51 +00:00
chip.c	soc/intel: Replace open-coded buffer length calculation	2021-04-21 14:21:44 +00:00
chip.h	soc/intel/alderlake/romstage: Update display UPDs based on InternalGfx	2021-06-16 03:50:20 +00:00
chipset.cb	soc/intel/adl: Add SKU specific power limits support	2021-06-07 19:02:02 +00:00
cpu.c	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
crashlog.c	soc/intel/alderlake: Add CrashLog implementation for Intel ADL	2021-05-06 03:32:22 +00:00
dptf.c	soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC	2021-04-23 14:46:33 +00:00
elog.c	soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros	2021-05-03 16:28:53 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c	soc/intel/*: drop useless XTAL shutdown qualification code	2020-10-19 07:09:12 +00:00
fsp_params.c	soc/intel/alderlake: Use devfn_disable() function for XDCI	2021-06-23 08:26:27 +00:00
gpio.c	soc/intel/alderlake: Add known GPIO virtual wire information	2021-05-14 08:58:07 +00:00
gspi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
i2c.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Kconfig	cpu/x86: Default to PARALLEL_MP selected	2021-06-07 21:02:54 +00:00
lockdown.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Makefile.inc	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	2021-05-18 16:54:21 +00:00
me.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
meminit.c	soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwards	2021-05-16 22:17:52 +00:00
p2sb.c	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	2020-09-15 15:13:50 +00:00
pcie_rp.c	soc/intel/alderlake: Update PCH and CPU PCIe RP table	2021-01-18 07:28:51 +00:00
pmc.c	soc/intel/alderlake: Add PMC ACPI interface	2021-06-04 16:33:53 +00:00
pmutil.c	soc/intel/*/pmutil.c: Align cosmetics across platforms	2021-02-24 11:34:42 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmaster	2021-05-07 06:05:18 +00:00
soundwire.c	soc/intel/alderlake: Update soundwire master count	2021-05-26 16:08:20 +00:00
spi.c	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
systemagent.c	soc/intel/adl: Add SKU specific power limits support	2021-06-07 19:02:02 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c	soc/intel/alderlake: Correct TCSS XHCI Port status offset	2021-06-08 15:25:29 +00:00