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coreboot-kgpe-d16/src/soc/intel/cannonlake/lockdown.c

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soc/intel/cannonlake: Use SPDX for GPL-2.0-only files Done with sed and God Lines. Only done for C-like code for now. Change-Id: I48422453735d50eb9292f39a3c031073d647a17c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05 15:46:52 +02:00
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
device/mmio.h: Add include file for MMIO ops MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03 07:01:05 +01:00
#include <device/mmio.h>
soc/intel: Rename <intelblocks/chip.h> The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-27 23:00:30 +02:00
#include <intelblocks/cfg.h>
soc/intel/cannonlake: lockdown: lock global reset There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17 18:48:00 +02:00
#include <intelblocks/pmclib.h>
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
#include <intelpch/lockdown.h>
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
#include <soc/pm.h>
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
static void pmc_lock_pmsync(void)
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
{
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
uint8_t *pmcbase;
uint32_t pmsyncreg;
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
pmcbase = pmc_mmio_regs();
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
soc/intel/common/block: Add common chip config block Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-09 11:25:09 +02:00
pmsyncreg |= PCH2CPU_TPR_CFG_LOCK;
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
}
static void pmc_lock_abase(void)
{
uint8_t *pmcbase;
uint32_t reg32;
pmcbase = pmc_mmio_regs();
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
reg32 = read32(pmcbase + GEN_PMCON_B);
reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
write32(pmcbase + GEN_PMCON_B, reg32);
}
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
static void pmc_lock_smi(void)
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
{
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
uint8_t *pmcbase;
uint8_t reg8;
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
pmcbase = pmc_mmio_regs();
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
reg8 = read8(pmcbase + GEN_PMCON_B);
reg8 |= SMI_LOCK;
write8(pmcbase + GEN_PMCON_B, reg8);
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
}
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
static void pmc_lockdown_cfg(int chipset_lockdown)
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
{
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
/* PMSYNC */
pmc_lock_pmsync();
/* Lock down ABASE and sleep stretching policy */
pmc_lock_abase();
soc/intel/cannonlake: lockdown: lock global reset There are four chipsets selecting PMC_GLOBAL_RESET_ENABLE_LOCK but only one (apollolake) is actually calling the code. Add the missing call. Change-Id: I6aba9bcb2ad09e6ae0e02d8c0b552e34bdb3fa72 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36571 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-17 18:48:00 +02:00
/* Make sure payload/OS can't trigger global reset */
pmc_global_reset_disable_and_lock();
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT)
pmc_lock_smi();
}
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
void soc_lockdown_config(int chipset_lockdown)
{
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
/* PMC lock down configuration */
soc/intel/common/pch: Add pch lockdown code pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-28 12:42:03 +02:00
pmc_lockdown_cfg(chipset_lockdown);
soc/intel/cannonlake: Add finalize function Before OS boot up, the following actions need to be taken. 1. Lock down PMC/SPI/DMI/TCO register. 2. Disable Sideband Access. 3. Disable Heci interface. 4. Disable PMtimer base on config settings. TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp board. Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21943 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 03:26:18 +02:00
}
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