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coreboot-kgpe-d16/src/mainboard/google/hatch/chromeos-hatch-16MiB.fmd

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mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
FLASH@0xff000000 0x1000000 {
SI_ALL@0x0 0x400000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0x3ff000
}
SI_BIOS@0x400000 0xc00000 {
mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOS The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-04 19:36:19 +02:00
RW_SECTION_A@0x0 0x368000 {
mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
VBLOCK_A@0x0 0x10000
mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOS The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-04 19:36:19 +02:00
FW_MAIN_A(CBFS)@0x10000 0x357fc0
RW_FWID_A@0x367fc0 0x40
mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
}
mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOS The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-04 19:36:19 +02:00
RW_SECTION_B@0x368000 0x368000 {
mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
VBLOCK_B@0x0 0x10000
mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOS The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-04 19:36:19 +02:00
FW_MAIN_B(CBFS)@0x10000 0x357fc0
RW_FWID_B@0x367fc0 0x40
mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
}
mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOS The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-04 19:36:19 +02:00
RW_MISC@0x6D0000 0x30000 {
mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
UNIFIED_MRC_CACHE@0x0 0x20000 {
RECOVERY_MRC_CACHE@0x0 0x10000
RW_MRC_CACHE@0x10000 0x10000
}
RW_ELOG(PRESERVE)@0x20000 0x4000
RW_SHARED@0x24000 0x4000 {
SHARED_DATA@0x0 0x2000
VBLOCK_DEV@0x2000 0x2000
}
RW_VPD(PRESERVE)@0x28000 0x2000
RW_NVRAM(PRESERVE)@0x2a000 0x6000
}
mb/google/hatch: Increase RW_LEGACY to 1M for 16MB BIOS The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS region, we had this region set too small, which was causing the firmware_FMap FAFT test to fail. BUG=b:133857135, b:129464811 BRANCH=None TEST=test_that -b hatch <IP> firmware_FMap Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-06-04 19:36:19 +02:00
# RW_LEGACY needs to be minimum of 1MB
RW_LEGACY(CBFS)@0x700000 0x100000
mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
WP_RO@0x800000 0x400000 {
RO_VPD(PRESERVE)@0x0 0x4000
RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800
RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0
mb/google: Shrink GBB section size Chrome OS firmware images have moved bitmap resources from GBB into CBFS for a long time, so the GBB should only hold firmware keys and HWID, that is usually less than 10k. ARM boards usually limit GBB to 0x2f00 (see gru, cheza and kukui) but many recent x86 simply copy from old settings and may run out of space when we want to add more resources, for example EC RO software sync. Note, changing the GBB section (inside RO) implies RO update, so this change *must not* be cherry-picked back to old firmware branches if some devices were already shipped. BRANCH=none BUG=None TEST=make # board=darllion,hatch,kahlee,octopus,sarien Change-Id: I615cd7b53b556019f2d54d0df7ac2723d36ee6cf Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-17 06:42:28 +02:00
GBB@0x1000 0x3000
COREBOOT(CBFS)@0x4000 0x3f8000
mb/google/hatch: Support 16MiB fmap Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-06 00:26:13 +02:00
}
}
}
}
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