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coreboot-kgpe-d16/src/arch/x86/bootblock_simple.c

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SMP: Add arch-agnostic boot_cpu() We should not have x86 specific includes in lib/. Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5156 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-26 13:41:54 +01:00
#include <smp/node.h>
Enable user selectable bootblocks, and provide a bootblock that selects between "fallback" and "normal", in addition to the already present "fallback"-only bootblock. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-24 14:58:23 +01:00
#include <bootblock_common.h>
Replace hlt with halt() There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-29 10:38:17 +01:00
#include <halt.h>
Enable user selectable bootblocks, and provide a bootblock that selects between "fallback" and "normal", in addition to the already present "fallback"-only bootblock. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-24 14:58:23 +01:00
static void main(unsigned long bist)
{
if (boot_cpu()) {
Refactor bootblock initialisation Makes it a bit easier to implement mainboard-specific behaviour while executing the bootblock. Change-Id: I04e87f89efb4fad1c0e20b62ea6a50329a286205 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1844 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-14 07:01:44 +01:00
bootblock_mainboard_init();
Move cmos.default handling to bootblock The cmos.default code wasn't actually used so far, due to an oversight when forward-porting this feature from an old branch. - Extend walkcbfs' use by factoring out the stage handling into C code. - New sanitize_cmos() function that looks if CMOS data is invalid and cmos.default exists and if so overwrites CMOS with cmos.default data. - Use sanitize_cmos() in both bootblock implementations. - Drop the need to reboot after writing CMOS: CMOS wasn't used so far, so we can go on without a reboot. - Remove the restriction that cmos.default only works on CAR boards. - Always build in cmos.default support on boards that USE_OPTION_TABLE. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 08:50:43 +01:00
#if CONFIG_USE_OPTION_TABLE
Only BSP CPU writes CMOS in bootblock code CMOS accesses are not safe for multi-processor and only the BSP CPU should count reboots and test CMOS sanity. A questionable single byte CMOS read access from AP CPUs remains. AP CPUs should always select the same romstage prefix as BSP CPU. Change-Id: I29118e33c07c0080c94abb90f703e38312c72432 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/446 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-05 19:17:17 +01:00
sanitize_cmos();
Add support for storing POST codes in CMOS This will use 3 bytes of CMOS to keep track of the POST code for the current boot while also leaving a record of the previous boot. The active bank is switched early in the bootblock. Test: 1) clear cmos 2) reboot 3) use "mosys nvram dump" to verify that the first byte contains 0x80 and the second byte contains 0xF8 4) powerd_suspend and then resume 5) use "mosys nvram dump" to verify that the first byte contains 0x81 and the second byte contains 0xFD Change-Id: I1ee6bb2dac053018f3042ab5a0b26c435dbfd151 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-09-10 04:09:56 +02:00
#endif
#if CONFIG_CMOS_POST
cmos_post_init();
Move cmos.default handling to bootblock The cmos.default code wasn't actually used so far, due to an oversight when forward-porting this feature from an old branch. - Extend walkcbfs' use by factoring out the stage handling into C code. - New sanitize_cmos() function that looks if CMOS data is invalid and cmos.default exists and if so overwrites CMOS with cmos.default data. - Use sanitize_cmos() in both bootblock implementations. - Drop the need to reboot after writing CMOS: CMOS wasn't used so far, so we can go on without a reboot. - Remove the restriction that cmos.default only works on CAR boards. - Always build in cmos.default support on boards that USE_OPTION_TABLE. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 08:50:43 +01:00
#endif
Only BSP CPU writes CMOS in bootblock code CMOS accesses are not safe for multi-processor and only the BSP CPU should count reboots and test CMOS sanity. A questionable single byte CMOS read access from AP CPUs remains. AP CPUs should always select the same romstage prefix as BSP CPU. Change-Id: I29118e33c07c0080c94abb90f703e38312c72432 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/446 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-05 19:17:17 +01:00
}
Move cmos.default handling to bootblock The cmos.default code wasn't actually used so far, due to an oversight when forward-porting this feature from an old branch. - Extend walkcbfs' use by factoring out the stage handling into C code. - New sanitize_cmos() function that looks if CMOS data is invalid and cmos.default exists and if so overwrites CMOS with cmos.default data. - Use sanitize_cmos() in both bootblock implementations. - Drop the need to reboot after writing CMOS: CMOS wasn't used so far, so we can go on without a reboot. - Remove the restriction that cmos.default only works on CAR boards. - Always build in cmos.default support on boards that USE_OPTION_TABLE. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 08:50:43 +01:00
x86: add standalone verstage support To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-29 23:31:20 +02:00
#if CONFIG_SEPARATE_VERSTAGE
const char* target1 = "fallback/verstage";
#else
Enable user selectable bootblocks, and provide a bootblock that selects between "fallback" and "normal", in addition to the already present "fallback"-only bootblock. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-24 14:58:23 +01:00
const char* target1 = "fallback/romstage";
x86: add standalone verstage support To support x86 verstage one needs a working buffer for vboot. That buffer resides in the cache-as-ram region which persists across verstage and romstage. The current assumption is that verstage brings cache-as-ram up and romstage tears cache-as-ram down. The timestamp, cbmem console, and the vboot work buffer are persistent through in both romstage and verstage. The vboot work buffer as well as the cbmem console are permanently destroyed once cache-as-ram is torn down. The timestamp region is migrated. When verstage is enabled the assumption is that _start is the romstage entry point. It's currently expected that the chipset provides the entry point to romstage when verstage is employed. Also, the car_var_*() APIs use direct access when in verstage since its expected verstage does not tear down cache-as-ram. Lastly, supporting files were added to verstage-y such that an x86 verstage will build and link. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados using separate verstage. Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11822 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-29 23:31:20 +02:00
#endif
Enable user selectable bootblocks, and provide a bootblock that selects between "fallback" and "normal", in addition to the already present "fallback"-only bootblock. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-24 14:58:23 +01:00
unsigned long entry;
entry = findstage(target1);
if (entry) call(entry, bist);
Replace hlt with halt() There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-29 10:38:17 +01:00
halt();
Enable user selectable bootblocks, and provide a bootblock that selects between "fallback" and "normal", in addition to the already present "fallback"-only bootblock. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5157 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-24 14:58:23 +01:00
}
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