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soc/intel/apollolake: Wrap lines at 80 columns 

Fix the following warning detected by checkpatch.pl:

WARNING: line over 80 characters

TEST=Build for reef

Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18728
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2017-03-09 10:59:25 -08:00 committed by Martin Roth
parent a444753596
commit 07441b5ae6
14 changed files with 69 additions and 52 deletions
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3
src/soc/intel/apollolake/acpi.c
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@ -64,7 +64,8 @@ static unsigned long acpi_madt_irq_overrides(unsigned long current)
current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
/* SCI */
current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags);
current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci,
flags);
return current;
}

2
src/soc/intel/apollolake/bootblock/cache_as_ram.S
View File

@ -157,7 +157,7 @@ clear_var_mtrr:
mov %eax, %ecx /* save to ecx */
mov $1, %ebx
shl %cl, %ebx
sub $1, %ebx /* resulting mask is is in ebx */
sub $1, %ebx /* resulting mask is is in ebx */
/* Set this mask for initial cache fill */
mov $MSR_L2_QOS_MASK(0), %ecx

4
src/soc/intel/apollolake/chip.c
View File

@ -488,7 +488,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable monitor mwait since it is broken due to a hardware bug without a fix */
/* Disable monitor mwait since it is broken due to a hardware bug
* without a fix
*/
silconfig->MonitorMwaitEnable = 0;
silconfig->SkipMpInit = 1;

6
src/soc/intel/apollolake/chip.h
View File

@ -62,14 +62,16 @@ struct soc_intel_apollolake_config {
/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
uint32_t emmc_tx_data_cntl2;
/* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
uint32_t emmc_rx_cmd_data_cntl1;

3
src/soc/intel/apollolake/flash_ctrlr.c
View File

@ -68,7 +68,8 @@ static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx)
}
/* Read register from the SPI flash controller. 'reg' is the register offset. */
static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, uint16_t reg)
static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx,
uint16_t reg)
{
uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4);
return read32((void *)addr);

3
src/soc/intel/apollolake/gpio.c
View File

@ -159,7 +159,8 @@ void gpio_configure_pad(const struct pad_config *cfg)
* This is done to preserve config1 size as unit16 in gpio.h.
*/
dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK;
dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) << PAD_CFG1_IOSSTATE_SHIFT;
dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK)
<< PAD_CFG1_IOSSTATE_SHIFT;
iosf_write(comm->port, config_offset, cfg->config0);
iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1);

6
src/soc/intel/apollolake/include/FspUpd.h
View File

@ -37,11 +37,11 @@ are permitted provided that the following conditions are met:
#pragma pack(push, 1)
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
#pragma pack(pop)

3
src/soc/intel/apollolake/include/soc/flash_ctrlr.h
View File

@ -50,7 +50,8 @@
#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK)
#define SPIBAR_HSFSTS_WET (1 << 21)
#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17)
#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK)
#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) \
& SPIBAR_HSFSTS_FCYCLE_MASK)
#define SPIBAR_HSFSTS_FGO (1 << 16)
#define SPIBAR_HSFSTS_FLOCKDN (1 << 15)
#define SPIBAR_HSFSTS_FDV (1 << 14)

3
src/soc/intel/apollolake/include/soc/gpio_defs.h
View File

@ -436,7 +436,8 @@
#define GPIO_COMM_SW_NAME "INT3452:03"
/* Default configurations */
#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP | PAD_CFG0_MODE_FUNC(x))
#define PAD_CFG0_DEFAULT_FUNC(x) (PAD_CFG0_RESET_DEEP \
| PAD_CFG0_MODE_FUNC(x))
#define PAD_CFG0_DEFAULT_NATIVE PAD_CFG0_DEFAULT_FUNC(1)
#define PAD_CFG1_DEFAULT_PULLUP PAD_CFG1_PULL_UP_20K

3
src/soc/intel/apollolake/include/soc/pci_devs.h
View File

@ -23,7 +23,8 @@
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#include <device/pci_def.h>
#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, \
func))
#define _PCI_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func))
#else
#include <arch/io.h>

24
src/soc/intel/apollolake/include/soc/pm.h
View File

@ -68,17 +68,19 @@
#define SMI_EOS 1
#define SMI_GBL 0
#define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */
#define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */
#define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */
#define GPIO_EN (1 << SMI_GPIO) /* Enable GPIO SMI */
#define BIOS_RLS (1 << SMI_BIOS_RLS) /* asserts SCI on bit set */
#define SWSMI_TMR_EN (1 << SMI_SWSMI_TMR) /* start software smi timer on bit set */
#define APMC_EN (1 << SMI_APMC) /* Writes to APM_CNT cause SMI# */
#define SLP_SMI_EN (1 << SMI_SLP) /* Write to SLP_EN in PM1_CNT asserts SMI# */
#define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */
#define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */
#define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */
#define USB_EN (1 << SMI_XHCI) /* Legacy USB2 SMI logic */
#define PERIODIC_EN (1 << SMI_PERIODIC) /* SMI on PERIODIC_STS in SMI_STS */
#define TCO_EN (1 << SMI_TCO) /* Enable TCO Logic (BIOSWE et al) */
#define GPIO_EN (1 << SMI_GPIO) /* Enable GPIO SMI */
#define BIOS_RLS (1 << SMI_BIOS_RLS) /* asserts SCI on bit set */
/* start software smi timer on bit set */
#define SWSMI_TMR_EN (1 << SMI_SWSMI_TMR)
#define APMC_EN (1 << SMI_APMC) /* Writes to APM_CNT cause SMI# */
/* Write to SLP_EN in PM1_CNT asserts SMI# */
#define SLP_SMI_EN (1 << SMI_SLP)
#define BIOS_EN (1 << SMI_BIOS) /* Assert SMI# on GBL_RLS bit */
#define EOS (1 << SMI_EOS) /* End of SMI (deassert SMI#) */
#define GBL_SMI_EN (1 << SMI_GBL) /* Global SMI Enable */
#define SMI_STS 0x44
/* Bits for SMI status */

48
src/soc/intel/apollolake/mmap_boot.c
View File

@ -30,29 +30,31 @@
* space. However, 256KiB right below 4GiB is decoded by read-only SRAM and not
* boot media.
*
* +----------------+ 0
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* +------------+ | |
* | IFD | | |
* bios_start +---> +------------+--------------------------> +----------------+ 4GiB - bios_size
* ^ | | ^ | |
* | | | | | |
* | | | bios_mapped_size | BIOS |
* | | BIOS | | | |
* bios_size | | | | |
* | | | v | |
* | | +--------------------------> +----------------+ 4GiB - 256KiB
* v | | | Read only SRAM |
* bios_end +---> +------------+ +----------------+ 4GiB
* | Device ext |
* +------------+
* +-----------+ 0
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* | |
* +--------+ | |
* | IFD | | |
* bios_start +---> +--------+------------------> +-----------+ 4GiB - bios_size
* ^ | | ^ | |
* | | | | | |
* | | | bios_mapped_size | BIOS |
* | | BIOS | | | |
* bios_size | | | | |
* | | | v | |
* | | +------------------> +-----------+ 4GiB - 256KiB
* | | | | Read only |
* v | | | SRAM |
* bios_end +---> +--------+ +-----------+ 4GiB
* | Device |
* | ext |
* +--------+
*
*/

7
src/soc/intel/apollolake/northbridge.c
View File

@ -105,14 +105,15 @@ static int mc_add_dram_resources(device_t dev, int index)
touud <<= 32;
touud |= ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB);
/* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */
/* 0 -> 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */
ram_resource(dev, index++, 0, 640);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_resource(dev, index++, 640, 128);
/* 0xc0000 -> 0xfffff: leave without e820 entry, as it has special uses */
/* 0x100000 -> top_of_ram */
/* 0xc0000 -> 0xfffff: leave without e820 entry, as it has special uses
* 0x100000 -> top_of_ram
*/
base_k = 1024;
size_k = (tseg / KiB) - base_k;
ram_resource(dev, index++, base_k, size_k);

6
src/soc/intel/apollolake/romstage.c
View File

@ -220,7 +220,8 @@ asmlinkage void car_stage_entry(void)
top_of_ram = (uintptr_t) cbmem_top();
/* cbmem_top() needs to be at least 16 MiB aligned */
assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB,
MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
@ -244,7 +245,8 @@ asmlinkage void car_stage_entry(void)
static void fill_console_params(FSPM_UPD *mupd)
{
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
mupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE;
mupd->FspmConfig.SerialDebugPortDevice =
CONFIG_UART_FOR_CONSOLE;
/* use MMIO port type */
mupd->FspmConfig.SerialDebugPortType = 2;
/* use 4 byte register stride */