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mainboard/intel/cannonlake_rvp: enable eMMC 

Set SCS emmc enable FSP parameter.

Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21409
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
This commit is contained in:
Bora Guvendik 2017-09-05 17:09:30 -07:00 committed by Aaron Durbin
parent 2d1e0eb8a7
commit 0a712c3337
2 changed files with 2 additions and 0 deletions
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1
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
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@ -8,6 +8,7 @@ chip soc/intel/cannonlake
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
device domain 0 on
device pci 00.0 on end # Host Bridge

1
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View File

@ -8,6 +8,7 @@ chip soc/intel/cannonlake
register "SaGv" = "3"
register "FspSkipMpInit" = "1"
register "SmbusEnable" = "1"
register "ScsEmmcEnabled" = "1"
device domain 0 on
device pci 00.0 on end # Host Bridge