Revert "soc/amd/cezanne/romstage: Preload fspm.bin"
This reverts commit d6e0a90aa0
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Reason for revert: Not ready to land, blocked by ancestor CL
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic14e17db4aed2f998878920c66cdc16362920dcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75050
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -18,8 +18,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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fsp_assign_vbios_upds(scfg);
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/*
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* At this point FSP-S has been loaded into RAM. Since FSP-S takes a while to execute
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* and performs no SPI operations, we can read the APOB while FSP-S executes.
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* At this point FSP-S has been loaded into RAM. If we were to start loading the APOB
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* before FSP-S was loaded, we would introduce contention onto the SPI bus and
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* slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs
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* no SPI operations, we can read the APOB while FSP-S executes.
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*/
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start_apob_cache_read();
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/*
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@ -18,8 +18,6 @@ void __noreturn romstage_main(void)
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/* Snapshot chipset state prior to any FSP call */
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fill_chipset_state();
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preload_fspm();
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fsp_memory_init(acpi_is_wakeup_s3());
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/* Fixup settings FSP-M should not be changing */
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