Revert "soc/amd/cezanne/romstage: Preload fspm.bin"

This reverts commit d6e0a90aa0.

Reason for revert: Not ready to land, blocked by ancestor CL

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic14e17db4aed2f998878920c66cdc16362920dcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75050
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/fsp_s_params.c

@@ -18,8 +18,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	fsp_assign_vbios_upds(scfg);
 
 	/*
-	 * At this point FSP-S has been loaded into RAM. Since FSP-S takes a while to execute
-	 * and performs no SPI operations, we can read the APOB while FSP-S executes.
+	 * At this point FSP-S has been loaded into RAM. If we were to start loading the APOB
+	 * before FSP-S was loaded, we would introduce contention onto the SPI bus and
+	 * slow down the FSP-S read from SPI. Since FSP-S takes a while to execute and performs
+	 * no SPI operations, we can read the APOB while FSP-S executes.
 	 */
 	start_apob_cache_read();
 	/*

src/soc/amd/cezanne/romstage.c

@@ -18,8 +18,6 @@ void __noreturn romstage_main(void)
 	/* Snapshot chipset state prior to any FSP call */
 	fill_chipset_state();
 
-	preload_fspm();
-
 	fsp_memory_init(acpi_is_wakeup_s3());
 
 	/* Fixup settings FSP-M should not be changing */