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AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins 

Some GPIO pins are shared with PCI bridge 0:14.4.

As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.

Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8495
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki 2014-11-11 17:22:23 +02:00
parent a6c7ae7014
commit 0b87bb7726
2 changed files with 2 additions and 1 deletions
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1
src/southbridge/amd/cimx/sb800/chip.h
View File

@ -35,6 +35,7 @@
struct southbridge_amd_cimx_sb800_config
{
u32 boot_switch_sata_ide : 1;
u32 disconnect_pcib : 1;
u8 gpp_configuration;
/*

2
src/southbridge/amd/cimx/sb800/late.c
View File

@ -401,7 +401,7 @@ static void sb800_enable(device_t dev)
* 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
* to function as GPIO {GPIO 35:0}.
*/
if (dev->enabled)
if (!sb_chip->disconnect_pcib && dev->enabled)
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
else
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);