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soc/mediatek/mt8188: Add DRAM fast calibration support 

Define fields of sdram_params and enable MEDIATEK_BLOB_FAST_INIT to
run fast calibration for MT8188 using blob.

DRAM fast calibration logs:
DRAM-K: Fast calibration passed in 19530 msecs
dram size (romstage): 0x200000000

TEST=Fast calibration pass.
BUG=b:233720142

Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2468d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Xi Chen 2022-07-26 10:57:32 +08:00 committed by Martin Roth
parent bcaa87d603
commit 0c4a39651d
2 changed files with 65 additions and 1 deletions
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1
src/soc/mediatek/mt8188/Kconfig
View File

@ -9,6 +9,7 @@ config SOC_MEDIATEK_MT8188
select SOC_MEDIATEK_COMMON select SOC_MEDIATEK_COMMON
select FLASH_DUAL_IO_READ select FLASH_DUAL_IO_READ
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select MEDIATEK_BLOB_FAST_INIT
if SOC_MEDIATEK_MT8188 if SOC_MEDIATEK_MT8188

65
src/soc/mediatek/mt8188/include/soc/dramc_param.h
View File

@ -21,7 +21,70 @@
#define DRAMC_PARAM_HEADER_VERSION 1 #define DRAMC_PARAM_HEADER_VERSION 1
struct sdram_params { struct sdram_params {
/* Not needed for full calibration */ /* rank, cbt */
u32 rank_num;
u32 dram_cbt_mode;
u16 delay_cell_timex100;
u8 u18ph_dly;
/* duty */
s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX];
s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP4 + 1];
s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP4];
/* cbt */
u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX];
u8 cbt_final_range[CHANNEL_MAX][RANK_MAX];
s16 cbt_cmd_dly[CHANNEL_MAX];
u16 cbt_cs_dly[CHANNEL_MAX];
u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER];
/* write leveling */
u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
/* gating */
u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
/* rx input buffer */
s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP4];
s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP4];
/* tx perbit */
u8 tx_window_vref[CHANNEL_MAX][RANK_MAX];
u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX];
u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
/* rx datlat */
u8 rx_datlat[CHANNEL_MAX][RANK_MAX];
/* rx perbit */
u8 rx_best_vref[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP4];
s16 rx_perbit_begin;
/* dcm */
u8 best_u[CHANNEL_MAX][RANK_MAX];
u8 best_l[CHANNEL_MAX][RANK_MAX];
/* tx oe */
u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP4];
u8 tx_oe_offset[CHANNEL_MAX][RANK_MAX];
/* imp k */
u8 sw_impedance[IMP_DRV_MAX];
}; };
struct dramc_data { struct dramc_data {