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soc/intel/skylake: Drop never-set DdrFreqLimit dt setting 

Only Google Eve uses a non-zero value, but it overwrites in C code.
Drop the devicetree setting, since no mainboard uses it.

Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Angel Pons 2020-12-11 16:57:50 +01:00
parent 86d195b192
commit 124e9f293b
2 changed files with 1 additions and 7 deletions
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6
src/soc/intel/skylake/chip.h
View File

@ -93,12 +93,6 @@ struct soc_intel_skylake_config {
/* Whether to ignore VT-d support of the SKU */ /* Whether to ignore VT-d support of the SKU */
int ignore_vtd; int ignore_vtd;
/*
* DDR Frequency Limit
* 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
*/
u16 DdrFreqLimit;
/* Probeless Trace function */ /* Probeless Trace function */
u8 ProbelessTrace; u8 ProbelessTrace;

2
src/soc/intel/skylake/romstage/romstage.c
View File

@ -221,7 +221,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->UserBd = BOARD_TYPE_ULT_ULX; m_cfg->UserBd = BOARD_TYPE_ULT_ULX;
m_cfg->RMT = config->Rmt; m_cfg->RMT = config->Rmt;
m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->CmdTriStateDis = config->CmdTriStateDis;
m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->DdrFreqLimit = 0;
m_cfg->VmxEnable = CONFIG(ENABLE_VMX); m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->PrmrrSize = get_valid_prmrr_size();
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {