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AMD MTRR: Add common add_uma_resource_below_tolm() 

Change-Id: I9eee88dc619ac5d9c77153db522a6ead65f6c9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kyösti Mälkki 2017-04-19 19:55:54 +03:00
parent a7dd645594
commit 17bb225be7
2 changed files with 20 additions and 0 deletions
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18
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -11,6 +11,7 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <arch/cpu.h> #include <arch/cpu.h>
@ -76,6 +77,23 @@ static void setup_ap_ramtop(void)
wrmsr(TOP_MEM2, msr); wrmsr(TOP_MEM2, msr);
} }
void add_uma_resource_below_tolm(struct device *nb, int idx)
{
uint32_t topmem = bsp_topmem();
uint32_t top_of_cacheable = get_top_of_ram();
if (top_of_cacheable == topmem)
return;
uint32_t uma_base = top_of_cacheable;
uint32_t uma_size = topmem - top_of_cacheable;
printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
__func__, uma_size, uma_base);
uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
}
void amd_setup_mtrrs(void) void amd_setup_mtrrs(void)
{ {
unsigned long address_bits; unsigned long address_bits;

2
src/include/cpu/amd/mtrr.h
View File

@ -41,6 +41,8 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
void amd_setup_mtrrs(void); void amd_setup_mtrrs(void);
struct device;
void add_uma_resource_below_tolm(struct device *nb, int idx);
static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index) static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
{ {