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mb/intel/adlrvp: Use HDA TMODE 8T to match spec for ADL P RVP 

With current setting Display audio codec probe fails.
Hence HDMI/DP audio fails.

Earlier, with FSP 2037 was used the mode was incorrectly programmed to 4T

This setting was carried ahead with below change:
Commit : 50f8b4ebdd

The issue was fixed in later FSPs and with current
FSP v2237, we need to set the TMODE to 8T as per spec.

TEST=Verify HDMI/DP Playback on ADL P RVP

Fixes: 50f8b4ebdd
       (soc/intel/alderlake: Add enum for HDA audio configuration)

Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56208
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sathya Prakash M R 2021-07-12 16:30:37 +05:30 committed by Subrata Banik
parent f9d7dc7ed3
commit 1f19ef54e4
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/intel/adlrvp/devicetree.cb
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@ -169,7 +169,7 @@ chip soc/intel/alderlake
# HD Audio # HD Audio
register "PchHdaDspEnable" = "1" register "PchHdaDspEnable" = "1"
register "PchHdaIDispLinkTmode" = "HDA_TMODE_4T" register "PchHdaIDispLinkTmode" = "HDA_TMODE_8T"
register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ" register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
register "PchHdaIDispCodecEnable" = "1" register "PchHdaIDispCodecEnable" = "1"