GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/braswell: Use Kconfig value for TSEG size 

SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also,
use SMM_TSEG_SIZE in place of a magic number.

Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Angel Pons 2020-12-11 17:44:08 +01:00
parent 233ae1919b
commit 20c8aa71d1
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/braswell/romstage/romstage.c
View File

@ -2,6 +2,7 @@
#include <cbmem.h>
#include <stdint.h>
#include <commonlib/helpers.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
@ -113,7 +114,7 @@ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd
config = config_of(dev);
printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? 8 : 0;
upd->PcdMrcInitTsegSize = CONFIG_SMM_TSEG_SIZE / MiB;
upd->PcdMrcInitMmioSize = 0x800;
upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;
upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2;