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mb/emulation/q35: Define pm_acpi_smi_cmd_port 

The X86 Qemu targets use the AMD64 SMM save state, but unlike
most AMD CPU's the PM ACPI SMI port is not configurable and uses
the Intel default APM_CNT, 0xb2 port.

This will be used by the common save state handler.

Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45814
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2020-09-29 11:52:57 +02:00 committed by Patrick Georgi
parent 3428027267
commit 27ba085334
2 changed files with 11 additions and 0 deletions
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2
src/mainboard/emulation/qemu-q35/Makefile.inc
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@ -14,3 +14,5 @@ ramstage-y += ../qemu-i440fx/northbridge.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c

9
src/mainboard/emulation/qemu-q35/smi.c Normal file
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@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/smm.h>
/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */
uint16_t pm_acpi_smi_cmd_port(void)
{
return APM_CNT;
}