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soc/intel/alderlake: fix NULL pointer dereference 

microcode_file could be NULL and passed to get_microcode_size,
this was detected by klocwork scan.

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Ibb3d49ab18d8c26bbf5d6bf6bdf1bf91137f5736
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Selma Bensaid 2021-10-11 16:37:36 -07:00 committed by Felix Held
parent c7ca0f2e33
commit 291294d137
1 changed files with 7 additions and 5 deletions
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12
src/soc/intel/alderlake/fsp_params.c
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@ -346,12 +346,14 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
/* Locate microcode and pass to FSP-S for 2nd microcode loading */
microcode_file = intel_microcode_find();
microcode_len = get_microcode_size(microcode_file);
if ((microcode_file != NULL) && (microcode_len != 0)) {
/* Update CPU Microcode patch base address/size */
s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file;
s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
if (microcode_file != NULL) {
microcode_len = get_microcode_size(microcode_file);
if (microcode_len != 0) {
/* Update CPU Microcode patch base address/size */
s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file;
s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
}
}
/* Use coreboot MP PPI services if Kconfig is enabled */