soc/amd: commonize PCI root IOAPIC initialization

Make the initialization of the IOAPIC(s) in the PCI root(s) common
across all AMD family 17h+ SoCs. For this the more general
implementation from the Genoa code that supports multiple PC roots is
moved to the common AMD code. All other family 17h+ SoCs are then
adapted to use the common code. For those non-Genoa SoCs, the
initialization of this second IOAPIC is moved from the northbridge
device to the domain device above to match Genoa.

Test=Both the FCH IOAPIC and the PCIe root IOAPIC are still initialized
on Mandolin

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c0ec6ac2f11cb11e46248cceec96c1fd2a49c16
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80286
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/chip.c

@@ -3,6 +3,7 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/fsp.h>
+#include <amdblocks/root_complex.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -29,6 +30,7 @@ struct device_operations cezanne_pci_domain_ops = {
 	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
 	.scan_bus	= amd_pci_domain_scan_bus,
+	.init		= amd_pci_domain_init,
 	.acpi_name	= soc_acpi_name,
 	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };

src/soc/amd/cezanne/root_complex.c

@@ -42,11 +42,6 @@ struct dptc_input {
 		},								\
 	}
 
-static void root_complex_init(struct device *dev)
-{
-	register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
-}
-
 static void acipgen_dptci(void)
 {
 	const struct soc_amd_cezanne_config *config = config_of_soc();
@@ -76,7 +71,6 @@ struct device_operations cezanne_root_complex_operations = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= root_complex_init,
 	.acpi_name		= gnb_acpi_name,
 	.acpi_fill_ssdt		= root_complex_fill_ssdt,
 };

src/soc/amd/common/block/include/amdblocks/root_complex.h

@@ -31,4 +31,6 @@ signed int get_iohc_fabric_id(struct device *domain);
 
 void read_fsp_resources(struct device *dev, unsigned long *idx);
 
+void amd_pci_domain_init(struct device *domain);
+
 #endif /* AMD_BLOCK_ROOT_COMPLEX_H */

src/soc/amd/common/block/root_complex/Makefile.mk

@@ -1,2 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
-ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX) += non_pci_resources.c
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX),y)
+
+ramstage-y += ioapic.c
+ramstage-y += non_pci_resources.c
+
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_ROOT_COMPLEX

src/soc/amd/common/block/root_complex/ioapic.c

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/ioapic.h>
+#include <amdblocks/root_complex.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <device/resource.h>
+#include <types.h>
+
+void amd_pci_domain_init(struct device *domain)
+{
+	struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
+	if (!res)
+		return;
+
+	register_new_ioapic((void *)(uintptr_t)res->base);
+}

src/soc/amd/genoa_poc/domain.c

@@ -42,15 +42,6 @@ static void genoa_domain_set_resources(struct device *domain)
 	}
 }
 
-static void genoa_domain_init(struct device *domain)
-{
-	struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
-	if (!res)
-		return;
-
-	register_new_ioapic((void *)(uintptr_t)res->base);
-}
-
 static const char *genoa_domain_acpi_name(const struct device *domain)
 {
 	const char *domain_acpi_names[4] = {
@@ -70,7 +61,7 @@ struct device_operations genoa_pci_domain_ops = {
 	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= genoa_domain_set_resources,
 	.scan_bus	= amd_pci_domain_scan_bus,
-	.init		= genoa_domain_init,
+	.init		= amd_pci_domain_init,
 	.acpi_name	= genoa_domain_acpi_name,
 	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };

src/soc/amd/glinda/chip.c

@@ -5,6 +5,7 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/fsp.h>
+#include <amdblocks/root_complex.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -31,6 +32,7 @@ struct device_operations glinda_pci_domain_ops = {
 	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
 	.scan_bus	= amd_pci_domain_scan_bus,
+	.init		= amd_pci_domain_init,
 	.acpi_name	= soc_acpi_name,
 	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };

src/soc/amd/glinda/root_complex.c

@@ -57,11 +57,6 @@ struct dptc_input {
 		},								\
 	}
 
-static void root_complex_init(struct device *dev)
-{
-	register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
-}
-
 static void acipgen_dptci(void)
 {
 	const struct soc_amd_glinda_config *config = config_of_soc();
@@ -106,7 +101,6 @@ struct device_operations glinda_root_complex_operations = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= root_complex_init,
 	.acpi_name		= gnb_acpi_name,
 	.acpi_fill_ssdt		= root_complex_fill_ssdt,
 };

src/soc/amd/mendocino/chip.c

@@ -3,6 +3,7 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/fsp.h>
+#include <amdblocks/root_complex.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -29,6 +30,7 @@ struct device_operations mendocino_pci_domain_ops = {
 	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
 	.scan_bus	= amd_pci_domain_scan_bus,
+	.init		= amd_pci_domain_init,
 	.acpi_name	= soc_acpi_name,
 	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };

src/soc/amd/mendocino/root_complex.c

@@ -85,11 +85,6 @@ struct dptc_input {
 		},								\
 	}
 
-static void root_complex_init(struct device *dev)
-{
-	register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
-}
-
 static void acipgen_dptci(void)
 {
 	const struct soc_amd_mendocino_config *config = config_of_soc();
@@ -267,7 +262,6 @@ struct device_operations mendocino_root_complex_operations = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= root_complex_init,
 	.acpi_name		= gnb_acpi_name,
 	.acpi_fill_ssdt		= root_complex_fill_ssdt,
 };

src/soc/amd/phoenix/chip.c

@@ -5,6 +5,7 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/fsp.h>
+#include <amdblocks/root_complex.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -32,6 +33,7 @@ struct device_operations phoenix_pci_domain_ops = {
 	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
 	.scan_bus	= amd_pci_domain_scan_bus,
+	.init		= amd_pci_domain_init,
 	.acpi_name	= soc_acpi_name,
 	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };

src/soc/amd/phoenix/root_complex.c

@@ -57,11 +57,6 @@ struct dptc_input {
 		},								\
 	}
 
-static void root_complex_init(struct device *dev)
-{
-	register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
-}
-
 static void acipgen_dptci(void)
 {
 	const struct soc_amd_phoenix_config *config = config_of_soc();
@@ -106,7 +101,6 @@ struct device_operations phoenix_root_complex_operations = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= root_complex_init,
 	.acpi_name		= gnb_acpi_name,
 	.acpi_fill_ssdt		= root_complex_fill_ssdt,
 };

src/soc/amd/picasso/chip.c

@@ -3,6 +3,7 @@
 #include <amdblocks/acpi.h>
 #include <amdblocks/data_fabric.h>
 #include <amdblocks/fsp.h>
+#include <amdblocks/root_complex.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -30,6 +31,7 @@ struct device_operations picasso_pci_domain_ops = {
 	.read_resources	= amd_pci_domain_read_resources,
 	.set_resources	= pci_domain_set_resources,
 	.scan_bus	= amd_pci_domain_scan_bus,
+	.init		= amd_pci_domain_init,
 	.acpi_name	= soc_acpi_name,
 	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };

src/soc/amd/picasso/root_complex.c

@@ -42,11 +42,6 @@ struct dptc_input {
 		},								\
 	}
 
-static void root_complex_init(struct device *dev)
-{
-	register_new_ioapic((u8 *)GNB_IO_APIC_ADDR);
-}
-
 static void acipgen_dptci(void)
 {
 	const struct soc_amd_picasso_config *config = config_of_soc();
@@ -85,7 +80,6 @@ struct device_operations picasso_root_complex_operations = {
 	.read_resources		= noop_read_resources,
 	.set_resources		= noop_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
-	.init			= root_complex_init,
 	.acpi_name		= gnb_acpi_name,
 	.acpi_fill_ssdt		= root_complex_fill_ssdt,
 };