soc/intel/{cnl,skl}: Add alignment check for TSEG base and size

Port commit 14d5991 (soc/intel/icelake: Add alignment check for TSEG
base and size) to remaining SoCs.

Change-Id: I90be6dfd3eb71ce66d6dfdcd711df061d880266f
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/cannonlake/smmrelocate.c

@@ -152,6 +152,12 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	const u32 rmask = ~(4 * KiB - 1);
 
 	smm_region(&tseg_base, &tseg_size);
+
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
+		printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n");
+		return;
+	}
+
 	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
 
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */

src/soc/intel/skylake/smmrelocate.c

@@ -152,6 +152,12 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 	const u32 rmask = ~(4 * KiB - 1);
 
 	smm_region(&tseg_base, &tseg_size);
+
+	if (!IS_ALIGNED(tseg_base, tseg_size)) {
+		printk(BIOS_WARNING, "TSEG base not aligned with TSEG size! Not setting SMRR\n");
+		return;
+	}
+
 	smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
 
 	/* SMRR has 32-bits of valid address aligned to 4KiB. */