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nb/intel/x4x: Use PCI bitwise ops 

Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.

Change-Id: I1bb7a7fd808cbbb45efbbfb9581c6a948323a48f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42155
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-06-08 01:39:25 +02:00 committed by Felix Held
parent 26886076f4
commit 4a9569a123
3 changed files with 10 additions and 18 deletions
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6
src/northbridge/intel/x4x/gma.c
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@ -48,11 +48,9 @@ static void gma_func0_init(struct device *dev)
static void gma_func0_disable(struct device *dev) static void gma_func0_disable(struct device *dev)
{ {
struct device *dev_host = pcidev_on_root(0, 0); struct device *dev_host = pcidev_on_root(0, 0);
u16 ggc;
ggc = pci_read_config16(dev_host, D0F0_GGC); /* VGA cycles to discrete GPU */
ggc |= (1 << 1); /* VGA cycles to discrete GPU */ pci_or_config16(dev_host, D0F0_GGC, 1 << 1);
pci_write_config16(dev_host, D0F0_GGC, ggc);
} }
static void gma_generate_ssdt(const struct device *device) static void gma_generate_ssdt(const struct device *device)

14
src/northbridge/intel/x4x/raminit.c
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@ -597,10 +597,9 @@ static void checkreset_ddr2(int boot_path)
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
/* do magic 0xf0 thing. */ /* do magic 0xf0 thing. */
u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2));
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2));
full_reset(); full_reset();
} }
@ -690,11 +689,10 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
do_raminit(&s, fast_boot); do_raminit(&s, fast_boot);
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~0x80);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);
pci_or_config8(PCI_DEV(0, 0, 0), 0xf4, 1);
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, reg8 | 1);
printk(BIOS_DEBUG, "RAM initialization finished.\n"); printk(BIOS_DEBUG, "RAM initialization finished.\n");
cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME); cbmem_was_inited = !cbmem_recovery(s.boot_path == BOOT_PATH_RESUME);

8
src/northbridge/intel/x4x/raminit_ddr23.c
View File

@ -1701,7 +1701,6 @@ static void configure_mmap(struct sysinfo *s)
u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,
160, 224, 352 }; 160, 224, 352 };
u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
u8 reg8;
ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; gfxsize = ggc2uma[(ggc & 0xf0) >> 4];
@ -1745,11 +1744,8 @@ static void configure_mmap(struct sysinfo *s)
pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20);
pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20);
/* Enable and set tseg size to 2M */ /* Enable and set TSEG size to 2M */
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); pci_update_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, ~0x07, (1 << 1) | (1 << 0));
reg8 &= ~0x7;
reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */
pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20);
} }