arch/riscv: Update comment about mstatus initialization

coreboot does not set up virtual memory anymore.

Change-Id: I231af07b2988e8362d1cdd606ce889fb31136ff1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/bootblock.S

@@ -66,7 +66,7 @@ _hart_zero:
 	# clear any pending interrupts
 	csrwi mip, 0
 
-	# set up the mstatus register for VM
+	# set up the mstatus register
 	call mstatus_init
 	tail main
 

src/arch/riscv/ramstage.S

@@ -43,7 +43,7 @@ _start:
 	csrwi mip, 0
 
 	call exit_car
-	# set up the mstatus register for VM
+	# set up the mstatus register
 	call mstatus_init
 	tail main