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soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPD 

Configure the S0i3 enable UPD based on the mainboard configuration.

BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.

Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Karthikeyan Ramasubramanian 2021-04-22 16:59:08 -06:00 committed by Patrick Georgi
parent 250e610fa0
commit 5ad85d95cd
1 changed files with 3 additions and 0 deletions
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3
src/soc/amd/cezanne/fsp_m_params.c
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@ -113,5 +113,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->cppc_epp_min_range = config->cppc_epp_min_range; mcfg->cppc_epp_min_range = config->cppc_epp_min_range;
mcfg->cppc_preferred_cores = config->cppc_preferred_cores; mcfg->cppc_preferred_cores = config->cppc_preferred_cores;
/* S0i3 enable */
mcfg->s0i3_enable = config->s0ix_enable;
fsp_fill_pcie_ddi_descriptors(mcfg); fsp_fill_pcie_ddi_descriptors(mcfg);
} }