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fsp1_0: Remove hardcoded microcode locations 

These are no longer needed.

Test: Booted minnowmax.

Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12468
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Martin Roth 2015-11-18 16:36:40 -07:00
parent d2e8f6ad33
commit 5cf5828c02
2 changed files with 0 additions and 9 deletions
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5
src/cpu/intel/fsp_model_406dx/Kconfig
View File

@ -53,11 +53,6 @@ config ENABLE_VMX
bool "Enable VMX for virtualization"
default n
config CPU_MICROCODE_CBFS_LOC
hex
depends on SUPPORT_CPU_UCODE_IN_CBFS
default 0xfff60040
config HAVE_CPU_MICROCODE_FILE
bool "Add microcode file"
help

4
src/soc/intel/fsp_baytrail/Kconfig
View File

@ -86,10 +86,6 @@ config VGA_BIOS_ID
This is the default PCI ID for the Bay Trail graphics
devices. This string names the vbios ROM in cbfs.
config CPU_MICROCODE_CBFS_LOC
hex
default 0xfff10040
config ENABLE_BUILTIN_COM1
bool "Enable built-in legacy Serial Port"
help