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mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2 

Due to mainboard restrictions a SATA link at Gen 3 can cause issues as
the margin is not big enough. Limit SATA speed to Gen 2 to achieve a
more robust SATA connection.

Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2023-05-22 14:45:42 +02:00 committed by Felix Held
parent f165bbdcf0
commit 6256fb63ff
3 changed files with 3 additions and 0 deletions
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1
src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
View File

@ -70,6 +70,7 @@ chip soc/intel/apollolake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "sata_speed" = "SATA_GEN2"
end
device pci 13.0 on # - RP 2 - PCIe A 0
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"

1
src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
View File

@ -70,6 +70,7 @@ chip soc/intel/apollolake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "sata_speed" = "SATA_GEN2"
end
device pci 13.0 on # - RP 2 - PCIe A 0
register "pcie_rp_clkreq_pin[2]" = "0"

1
src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
View File

@ -41,6 +41,7 @@ chip soc/intel/apollolake
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "DisableSataSalpSupport" = "1"
register "sata_speed" = "SATA_GEN2"
end
device pci 13.0 on # - RP 2 - PCIe A 0
register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"