mb/intel/mtlrvp: Add files required for ramstage and SMM
This patch adds files required for ramstage and SMM. 1. Add file required for ramstage (mainboard.c) 2. Add smihandler.c for SMM BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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## SPDX-License-Identifier: GPL-2.0-or-later
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ramstage-y += ec.c
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ramstage-y += mainboard.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
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BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <device/device.h>
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#include <drivers/intel/gma/opregion.h>
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#include <ec/ec.h>
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#include <ec/intel/board_id.h>
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#include <soc/ramstage.h>
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#include <smbios.h>
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#include <stdint.h>
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#include <string.h>
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const char *smbios_system_sku(void)
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{
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static char sku_str[7] = "";
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uint8_t sku_id = get_rvp_board_id();
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snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id);
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return sku_str;
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}
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const char *mainboard_vbt_filename(void)
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{
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return "vbt.bin";
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}
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void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *cfg)
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{
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/* TODO: Update mainboard */
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}
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static void mainboard_init(void *chip_info)
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{
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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mainboard_ec_init();
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}
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static void mainboard_enable(struct device *dev)
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{
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/* TODO: Enable mainboard */
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}
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struct chip_operations mainboard_ops = {
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.init = mainboard_init,
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.enable_dev = mainboard_enable,
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};
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <cpu/x86/smm.h>
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#include <ec/google/chromeec/smm.h>
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#include <intelblocks/smihandler.h>
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#include <baseboard/ec.h>
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void mainboard_smi_espi_handler(void)
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{
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if (!CONFIG(EC_GOOGLE_CHROMEEC))
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return;
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chromeec_smi_process_events();
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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if (!CONFIG(EC_GOOGLE_CHROMEEC))
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return;
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chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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if (CONFIG(EC_GOOGLE_CHROMEEC))
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chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
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return 0;
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}
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