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cpu/intel/socket_p: Increase DCACHE_RAM_SIZE 

The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.

This fixes building when some debug options are enabled.

Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Arthur Heymans 2021-05-05 14:46:14 +02:00
parent e69461dc25
commit 66538e0877
2 changed files with 1 additions and 2 deletions
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2
src/cpu/intel/socket_p/Kconfig
View File

@ -12,7 +12,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex hex
default 0x8000 default 0x10000
config DCACHE_BSP_STACK_SIZE config DCACHE_BSP_STACK_SIZE
hex hex

1
src/mainboard/lenovo/t400/Kconfig
View File

@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500 select MAINBOARD_USES_IFD_GBE_REGION if !BOARD_LENOVO_R500
select INTEL_GMA_HAVE_VBT select INTEL_GMA_HAVE_VBT
select NO_CBFS_MCACHE
config VBOOT config VBOOT
select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS