memory_info.h: Store SMBIOS error correction type
There are platforms that support error correction types other than single-bit ECC. Extend meminfo to accomodate additional ECC types. It is assumed that `struct memory_info` is packed to save space. Thus, use `uint8_t` instead of an enum type (which are usually 4 bytes wide). Change-Id: I863f8e34c84841d931dfb8d7067af0f12a437e36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50178 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -445,8 +445,7 @@ static int get_socket_type(void)
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unsigned int __weak smbios_memory_error_correction_type(struct memory_info *meminfo)
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{
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return meminfo->ecc_capable ?
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MEMORY_ARRAY_ECC_SINGLE_BIT : MEMORY_ARRAY_ECC_NONE;
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return meminfo->ecc_type;
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}
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unsigned int __weak smbios_processor_external_clock(void)
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@ -96,8 +96,11 @@ struct dimm_info {
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} __packed;
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struct memory_info {
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/* controller specific */
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bool ecc_capable;
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/*
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* SMBIOS error correction type.
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* See the smbios.h smbios_memory_array_ecc enum.
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*/
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uint8_t ecc_type;
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/* Maximum capacity the DRAM controller/mainboard supports */
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uint32_t max_capacity_mib;
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/* Maximum number of DIMMs the DRAM controller/mainboard supports */
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@ -167,9 +167,9 @@ void sdram_initialize(struct pei_data *pei_data)
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report_memory_config();
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}
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static bool nb_supports_ecc(const uint32_t capid0_a)
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static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
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{
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return !(capid0_a & CAPID_ECCDIS);
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return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
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}
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static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
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@ -256,7 +256,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data)
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const uint16_t channels = nb_number_of_channels(capid0_a);
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mem_info->ecc_capable = nb_supports_ecc(capid0_a);
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mem_info->ecc_type = nb_get_ecc_type(capid0_a);
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mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
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mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
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}
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@ -53,9 +53,9 @@ static void disable_channel(ramctr_timing *ctrl, int channel)
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memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0]));
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}
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static bool nb_supports_ecc(const uint32_t capid0_a)
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static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
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{
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return !(capid0_a & CAPID_ECCDIS);
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return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
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}
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static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
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@ -114,7 +114,7 @@ static void setup_sdram_meminfo(ramctr_timing *ctrl)
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const uint16_t channels = nb_number_of_channels(capid0_a);
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m->ecc_capable = nb_supports_ecc(capid0_a);
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m->ecc_type = nb_get_ecc_type(capid0_a);
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m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
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m->number_of_devices = channels * nb_slots_per_channel(capid0_a);
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}
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@ -48,9 +48,9 @@ __weak uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
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return 32768; /* 32 GiB per channel */
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}
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static bool sa_supports_ecc(const uint32_t capid0_a)
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static uint8_t sa_get_ecc_type(const uint32_t capid0_a)
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{
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return !(capid0_a & CAPID_ECCDIS);
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return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
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}
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static size_t sa_slots_per_channel(const uint32_t capid0_a)
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@ -73,7 +73,7 @@ static void sa_soc_systemagent_init(struct device *dev)
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const uint32_t capid0_a = pci_read_config32(dev, CAPID0_A);
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m->ecc_capable = sa_supports_ecc(capid0_a);
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m->ecc_type = sa_get_ecc_type(capid0_a);
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m->max_capacity_mib = soc_systemagent_max_chan_capacity_mib(CAPID_DDRSZ(capid0_a)) *
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sa_number_of_channels(capid0_a);
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m->number_of_devices = sa_slots_per_channel(capid0_a) *
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