mb/hp: Add new port for compaq_8300_elite_usdt
New port based on autoport. Autoport worked with minor tweaks, but fan speeds went almost immediately to the maximum. They are controlled by the NPCD379 Super I/O which isn't supported by coreboot. But coreboot already has code for NPCD378, which HP Compaq 8200 SFF makes use of. So SuperIO configuration was copied from the 8200 SFF port. It seems to work without any issues in "normal" use. Most importantly, fan speed control seems to work correctly. However this means that some of the SuperIO LDNs may be configured incorrectly. See the comments on Gerrit for more information. The following is tested and is working: * Native raminit with both DIMMs * Libgfxinit textmode and framebuffer on both DisplayPorts and VGA * External USB2 and USB3 ports: they all work * USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports) * Ethernet * Mini-PCIe WLAN * SATA: 2.5" SSD and optical drive bay * Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1 * GRUB (with Libreboot config) * PS/2 keyboard and mouse * S3 suspend and resume, wake using USB keyboard * Headphone output, line out, internal speaker * Wake on LAN * Rebooting * CMOS options & nvramcui Untested: * mSATA slot. The SATA port needs to be enabled on devicetree too, but I'm unable to test due to lack of hardware * Line in, mic input * MXM graphics card * EHCI debug Not working: * Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so maybe it just isn't present * PS/2 keyboard wake from S3 Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3 Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Riku Viitanen
Kyösti Mälkki
parent
8d16a14367
commit
685097ba3b
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# HP Compaq 8300 Elite USDT
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This page describes how to run coreboot on the [Compaq 8300 Elite USDT] desktop
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from [HP].
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## Flashing coreboot
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```eval_rst
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+---------------------+-------------+
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| Type | Value |
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+=====================+=============+
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| Socketed flash | no |
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+---------------------+-------------+
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| Model | W25Q128BVFG |
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+---------------------+-------------+
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| Size | 16 MiB |
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+---------------------+-------------+
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| In circuit flashing | yes |
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+---------------------+-------------+
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| Package | SOIC-16 |
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+---------------------+-------------+
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| Write protection | No |
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+---------------------+-------------+
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| Dual BIOS feature | No |
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+---------------------+-------------+
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```
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### Internal programming
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TODO: investigate
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The board has two jumpers that might be relevant: FDO (Flash Descriptor Override) and BB (?).
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### External programming
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Remove the lid. The flash chip can be found on the edge opposite to the CPU.
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There is a spot for a "ROM RCVRY" header next to the flash chip but it is
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unpopulated. If you don't feel like using a clip, you can easily solder
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a standard pin header there yourself and use it for programming.
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Programming powers some parts of the board. Programming when
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Wake on LAN is active works great.
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
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+------------------+--------------------------------------------------+
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| Southbridge | bd82x6x |
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+------------------+--------------------------------------------------+
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| CPU | model_206ax |
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+------------------+--------------------------------------------------+
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| SuperIO | NPCD379HAKFX |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel ME |
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+------------------+--------------------------------------------------+
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```
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### SuperIO
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This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
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fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
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[Compaq 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
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[HP]: https://www.hp.com/
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Binary file not shown.
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After Width: | Height: | Size: 148 KiB |
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@ -0,0 +1,38 @@
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if BOARD_HP_COMPAQ_ELITE_8300_USDT
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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select INTEL_INT15
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select MAINBOARD_HAS_TPM1
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select MAINBOARD_HAS_LIBGFXINIT
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select MAINBOARD_USES_IFD_GBE_REGION
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select MEMORY_MAPPED_TPM
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_NUVOTON_NPCD378
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select USE_NATIVE_RAMINIT
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config CBFS_SIZE
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default 0x570000
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config MAINBOARD_DIR
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default "hp/compaq_elite_8300_usdt"
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config MAINBOARD_PART_NUMBER
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default "HP Compaq Elite 8300 USDT"
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config VGA_BIOS_ID
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default "8086,0152"
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config DRAM_RESET_GATE_GPIO
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default 60
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config USBDEBUG_HCD_INDEX # FIXME: check this
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default 2
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endif
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@ -0,0 +1,2 @@
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config BOARD_HP_COMPAQ_ELITE_8300_USDT
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bool "Compaq Elite 8300 USDT"
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bootblock-y += early_init.c
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bootblock-y += gpio.c
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romstage-y += early_init.c
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romstage-y += gpio.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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@ -0,0 +1 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* SPDX-License-Identifier: GPL-2.0-only */
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Method(_WAK, 1)
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{
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Return(Package() {0, 0})
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}
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Method(_PTS, 1)
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{
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */
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#include <superio/nuvoton/npcd378/acpi/superio.asl>
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Scope (\_GPE)
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{
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Method (_L0D, 0, NotSerialized)
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{
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Notify (\_SB.PCI0.EHC1, 0x02)
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Notify (\_SB.PCI0.EHC2, 0x02)
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//FIXME: Add GBE device
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//Notify (\_SB.PCI0.GBE, 0x02)
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}
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Method (_L09, 0, NotSerialized)
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{
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Notify (\_SB.PCI0.RP01, 0x02)
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Notify (\_SB.PCI0.RP02, 0x02)
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Notify (\_SB.PCI0.RP03, 0x02)
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Notify (\_SB.PCI0.RP04, 0x02)
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Notify (\_SB.PCI0.RP05, 0x02)
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Notify (\_SB.PCI0.RP06, 0x02)
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Notify (\_SB.PCI0.RP07, 0x02)
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Notify (\_SB.PCI0.RP08, 0x02)
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Notify (\_SB.PCI0.PEGP, 0x02)
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}
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi_gnvs.h>
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#include <soc/nvs.h>
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void mainboard_fill_gnvs(struct global_nvs *gnvs)
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{
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/* Temperature at which OS will shutdown */
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gnvs->tcrt = 100;
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/* Temperature at which OS will throttle CPU */
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gnvs->tpsv = 90;
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}
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Category: mini
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ROM protocol: SPI
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ROM socketed: n
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ROM package: SOIC-16
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Flashrom support: y
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Release year: 2012
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Enable
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nmi=Enable
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sata_mode=AHCI
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gfx_uma_size=32M
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## SPDX-License-Identifier: GPL-2.0-only
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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# -----------------------------------------------------------------
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# coreboot config options: console
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395 4 e 6 debug_level
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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421 1 e 9 sata_mode
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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448 128 r 0 vbnv
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 0 Emergency
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6 1 Alert
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6 2 Critical
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6 3 Error
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6 4 Warning
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6 5 Notice
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6 6 Info
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6 7 Debug
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6 8 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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9 0 AHCI
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9 1 IDE
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11 0 32M
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11 1 64M
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11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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11 6 224M
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# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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chip northbridge/intel/sandybridge
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register "gpu_dp_b_hotplug" = "4"
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register "gpu_dp_c_hotplug" = "4"
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "docking_supported" = "0"
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register "gen1_dec" = "0x00fc0a01"
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register "gen2_dec" = "0x00fc0801"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3" # 0x1: 2.5" slot
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# 0x2: DVD
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# 0x?: mSATA
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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register "superspeed_capable_ports" = "0x0000000f"
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register "xhci_overcurrent_mapping" = "0x00000c03"
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register "xhci_switchable_ports" = "0x0000000f"
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device ref xhci on # USB 3.0 Controller
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subsystemid 0x103c 0x3398
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end
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device ref mei1 off # Management Engine Interface 1
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end
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device ref gbe on # Intel Gigabit Ethernet
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subsystemid 0x103c 0x3398
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end
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device ref ehci2 on # USB2 EHCI #2
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subsystemid 0x103c 0x3398
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end
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device ref hda on # High Definition Audio
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subsystemid 0x103c 0x3398
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end
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device ref pcie_rp1 on # Mini-PCIe WLAN
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end
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device ref ehci1 on # USB2 EHCI #1
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subsystemid 0x103c 0x3398
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end
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device ref pci_bridge on # PCI bridge
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subsystemid 0x103c 0x3398
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end
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device ref lpc on # LPC bridge
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chip superio/common # Super I/O grabbed from 8200SFF devicetree
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device pnp 2e.ff on # passes SIO base addr to SSDT gen
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chip superio/nuvoton/npcd378
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 off end # Parallel
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device pnp 2e.2 off # COM1
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # COM2, IR
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.4 on # LED control
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io 0x60 = 0x600
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# IOBASE[0h] = bit0 LED red / green
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# IOBASE[0h] = bit1-4 LED PWM duty cycle
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# IOBASE[1h] = bit6 SWCC
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io 0x62 = 0x610
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# IOBASE [0h] = GPES
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# IOBASE [1h] = GPEE
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# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
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# IOBASE [8h:bh] = GPS
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# IOBASE [ch:fh] = GPE
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end
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device pnp 2e.5 on # Mouse
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irq 0x70 = 0xc
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end
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device pnp 2e.6 on # Keyboard
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io 0x60 = 0x0060
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io 0x62 = 0x0064
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irq 0x70 = 0x01
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# serialice: Vendor writes:
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drq 0xf0 = 0x40
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end
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device pnp 2e.7 on # WDT ?
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io 0x60 = 0x620
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end
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device pnp 2e.8 on # HWM
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io 0x60 = 0x800
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# IOBASE[0h:feh] HWM page
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# IOBASE[ffh] bit0-bit3 page selector
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drq 0xf0 = 0x20
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drq 0xf1 = 0x01
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drq 0xf2 = 0x40
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drq 0xf3 = 0x01
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drq 0xf4 = 0x66
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drq 0xf5 = 0x67
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drq 0xf6 = 0x66
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drq 0xf7 = 0x01
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end
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device pnp 2e.f on # GPIO OD ?
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drq 0xf1 = 0x97
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drq 0xf2 = 0x01
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drq 0xf5 = 0x08
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drq 0xfe = 0x80
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end
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device pnp 2e.15 on # BUS ?
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io 0x60 = 0x0680
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io 0x62 = 0x0690
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end
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device pnp 2e.1c on # Suspend Control ?
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io 0x60 = 0x640
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# writing to IOBASE[5h]
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# 0x0: Power off
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# 0x9: Power off and bricked until CMOS battery removed
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end
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device pnp 2e.1e on # GPIO ?
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io 0x60 = 0x660
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drq 0xf4 = 0x01
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# skip the following, as it
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# looks like remapped registers
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#drq 0xf5 = 0x06
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#drq 0xf6 = 0x60
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#drq 0xfe = 0x03
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end
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end
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end
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end
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chip drivers/pc80/tpm
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device pnp 4e.0 on end # TPM module
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end
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end
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device ref sata1 on # SATA Controller 1
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subsystemid 0x103c 0x3398
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end
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device ref smbus on # SMBus
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subsystemid 0x103c 0x3398
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end
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end
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device ref host_bridge on # Host bridge Host bridge
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subsystemid 0x103c 0x3398
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end
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device ref peg10 on end # PEG
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device ref igd on # iGPU
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subsystemid 0x103c 0x3398
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end
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <acpi/acpi.h>
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#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
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#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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ACPI_DSDT_REV_2,
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20141018 /* OEM revision */
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)
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{
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#include <acpi/dsdt_top.asl>
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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||||
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
}
|
||||
}
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|
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/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
#include <bootblock_common.h>
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||||
#include <superio/nuvoton/npcd378/npcd378.h>
|
||||
#include <superio/nuvoton/common/nuvoton.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
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||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
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{ 1, 0, 0 },
|
||||
{ 1, 0, 0 },
|
||||
{ 1, 0, 1 },
|
||||
{ 1, 0, 1 },
|
||||
{ 1, 0, 2 },
|
||||
{ 1, 0, 2 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 0, 3 },
|
||||
{ 1, 0, 4 },
|
||||
{ 1, 0, 4 },
|
||||
{ 1, 0, 6 },
|
||||
{ 1, 0, 5 },
|
||||
{ 1, 0, 5 },
|
||||
{ 1, 0, 6 },
|
||||
};
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408);
|
||||
pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[3], 0x50, id_only);
|
||||
read_spd(&spd[1], 0x52, id_only);
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(DP1,
|
||||
DP2,
|
||||
HDMI1,
|
||||
HDMI2,
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,191 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_NATIVE,
|
||||
.gpio3 = GPIO_MODE_NATIVE,
|
||||
.gpio4 = GPIO_MODE_NATIVE,
|
||||
.gpio5 = GPIO_MODE_NATIVE,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_NATIVE,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_NATIVE,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio11 = GPIO_DIR_INPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_OUTPUT,
|
||||
.gpio21 = GPIO_DIR_INPUT,
|
||||
.gpio22 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_INPUT,
|
||||
.gpio27 = GPIO_DIR_INPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio17 = GPIO_LEVEL_LOW,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio0 = GPIO_INVERT,
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio6 = GPIO_INVERT,
|
||||
.gpio11 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_GPIO,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_GPIO,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_GPIO,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_INPUT,
|
||||
.gpio33 = GPIO_DIR_INPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_INPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio43 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio54 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
.gpio61 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_OUTPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio71 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0221, /* Codec Vendor / Device ID: Realtek */
|
||||
0x103c3398, /* Subsystem ID */
|
||||
11, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0, 0x103c3398),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x01014020),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x598301f0),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
|
||||
|
||||
0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
0x80860101, /* Subsystem ID */
|
||||
4, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
AZALIA_PIN_CFG(3, 0x07, 0x58560030),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
Loading…
Reference in New Issue