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soc/amd/stoneyridge: Add IGFX device ACPI ASL entry 

Add internal graphics device 00.01.00 to the ACPI tables so that the
ACPI PCI option ROM save functions have a proper scope to save the
ROM to.

BUG=b:111697181
TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope"
and check _ROM method is added in the SSDT1.

Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Marc Jones 2018-07-26 17:07:13 -06:00 committed by Marc Jones
parent bd21f2844b
commit 6dcb6c2fa4
2 changed files with 7 additions and 0 deletions
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5
src/soc/amd/stoneyridge/acpi/northbridge.asl
View File

@ -46,6 +46,11 @@ Device(AMRT) {
Name(_ADR, 0x00000000) Name(_ADR, 0x00000000)
} /* end AMRT */ } /* end AMRT */
/* Internal Graphics */
Device(IGFX) {
Name(_ADR, 0x00010000)
}
/* Gpp 0 */ /* Gpp 0 */
Device(PBR4) { Device(PBR4) {
Name(_ADR, 0x00020001) Name(_ADR, 0x00020001)

2
src/soc/amd/stoneyridge/chip.c
View File

@ -82,6 +82,8 @@ const char *soc_acpi_name(const struct device *dev)
return NULL; return NULL;
switch (dev->path.pci.devfn) { switch (dev->path.pci.devfn) {
case GFX_DEVFN:
return "IGFX";
case PCIE0_DEVFN: case PCIE0_DEVFN:
return "PBR4"; return "PBR4";
case PCIE1_DEVFN: case PCIE1_DEVFN: