GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/cannonlake: Fix GEN_PMCON bit checks 

CNL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.

BUG=b:128482282
TEST=Verified that prev_sleep_state is reported correctly when booting
from S5.

Change-Id: I75780a004ded8f282ffb3feb0cdc76233ebfd4f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2019-03-14 15:44:19 -07:00
parent 90a96c77a9
commit 6e401cf7e6
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/cannonlake/elog.c
View File

@ -76,11 +76,11 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_THERM_TRIP); elog_add_event(ELOG_TYPE_THERM_TRIP);
/* PWR_FLR Power Failure */ /* PWR_FLR Power Failure */
if (ps->gen_pmcon_b & PWR_FLR) if (ps->gen_pmcon_a & PWR_FLR)
elog_add_event(ELOG_TYPE_POWER_FAIL); elog_add_event(ELOG_TYPE_POWER_FAIL);
/* SUS Well Power Failure */ /* SUS Well Power Failure */
if (ps->gen_pmcon_b & SUS_PWR_FLR) if (ps->gen_pmcon_a & SUS_PWR_FLR)
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
/* TCO Timeout */ /* TCO Timeout */
@ -97,7 +97,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_RTC_RESET); elog_add_event(ELOG_TYPE_RTC_RESET);
/* Host Reset Status */ /* Host Reset Status */
if (ps->gen_pmcon_b & HOST_RST_STS) if (ps->gen_pmcon_a & HOST_RST_STS)
elog_add_event(ELOG_TYPE_SYSTEM_RESET); elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake Event */ /* ACPI Wake Event */

4
src/soc/intel/cannonlake/pmutil.c
View File

@ -217,7 +217,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
* S5 because the PCH does not set the WAK_STS bit when waking * S5 because the PCH does not set the WAK_STS bit when waking
* from a true G3 state. * from a true G3 state.
*/ */
if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) if (ps->gen_pmcon_a & (PWR_FLR | SUS_PWR_FLR))
prev_sleep_state = ACPI_S5; prev_sleep_state = ACPI_S5;
/* /*
@ -233,7 +233,7 @@ int soc_prev_sleep_state(const struct chipset_power_state *ps,
if (!deep_s3_enabled()) if (!deep_s3_enabled())
mask |= SUS_PWR_FLR; mask |= SUS_PWR_FLR;
if (ps->gen_pmcon_b & mask) if (ps->gen_pmcon_a & mask)
prev_sleep_state = ACPI_S5; prev_sleep_state = ACPI_S5;
} }