soc/intel/alderlake: Implement PCH lock down configuration

This patch implements a function to enable IOSF Primary Trunk Clock
Gating.

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Subrata Banik 2022-04-18 13:31:57 +05:30 committed by Felix Held
parent bae4a0b5a1
commit 71fd0fa780
1 changed files with 17 additions and 0 deletions

View File

@ -8,10 +8,16 @@
#include <device/mmio.h> #include <device/mmio.h>
#include <intelblocks/cfg.h> #include <intelblocks/cfg.h>
#include <intelblocks/pcr.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h> #include <soc/pm.h>
#include <stdint.h> #include <stdint.h>
/* PCR PSTH Control Register */
#define PCR_PSTH_CTRLREG 0x1d00
#define PSTH_CTRLREG_IOSFPTCGE (1 << 2)
static void pmc_lockdown_cfg(int chipset_lockdown) static void pmc_lockdown_cfg(int chipset_lockdown)
{ {
uint8_t *pmcbase = pmc_mmio_regs(); uint8_t *pmcbase = pmc_mmio_regs();
@ -32,8 +38,19 @@ static void pmc_lockdown_cfg(int chipset_lockdown)
} }
} }
static void pch_lockdown_cfg(void)
{
if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM))
return;
/* Enable IOSF Primary Trunk Clock Gating */
pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE);
}
void soc_lockdown_config(int chipset_lockdown) void soc_lockdown_config(int chipset_lockdown)
{ {
/* PMC lock down configuration */ /* PMC lock down configuration */
pmc_lockdown_cfg(chipset_lockdown); pmc_lockdown_cfg(chipset_lockdown);
/* PCH lock down configuration */
pch_lockdown_cfg();
} }