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mainboard/ocp: Add support for OCP platform TiogaPass 

OCP platform Tiogapass is a 2-socket server platform, which
is based on a chipset including Intel Skylake-SP processors
and a Lewisburg PCH. Skylake-SP is a processor in Intel Xeon
Scalable Processor family.

Following ACPI tables are added:
DSDT/SSDT, MADT, FACP, FACS, HPET, MCFG, SLIT, SRAT, DMAR

This patchset is tested on a Tiogapass board. It booted with
Linux kernel 4.16.0; lscpu command shows all 72 cpus (2 sockets,
18 cores, 2 thread per core); ssh command shows
networking is up from Mellanox ConnectX-4 PCIe NIC card.

Towards successful gerrit buildbot build, note that:
* microcode is in coreboot intel-microcode submodule repo.
* IFD binary is included in this patch.
* Dummy ME binary is used, as it may take long time for Intel
ME binary to be available in public domain.
* Fake FSP binary is used, as at this moment the SKX-SP
FSP binary is not going to be available in public domain.

Known issues (Not intend to address in this initial support for
Xeon-SP processors):
* c6 state is not supported.
* dsdt table is not fully populated, such as processor/socket
devices, some PCIe devices.
* SMM handlers are not added.

Following are some command execution with CentOS booted from
local SATA disk:
[root@localhost ~]# lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                72
On-line CPU(s) list:   0-71
Thread(s) per core:    2
Core(s) per socket:    18
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 85
Model name:            Intel(R) Xeon(R) Gold 6139 CPU @ 2.30GHz
Stepping:              4
CPU MHz:               140.415
BogoMIPS:              4626.46
Virtualization:        VT-x
L1d cache:             32K
L1i cache:             32K
L2 cache:              1024K
L3 cache:              25344K
NUMA node0 CPU(s):     0-17,36-53
NUMA node1 CPU(s):     18-35,54-71
[root@localhost ~]# ifconfig
eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST>  mtu 1500
        inet 172.23.68.190  netmask 255.255.0.0  broadcast 172.23.255.255
        inet6 2620:10d:c082:9063:268a:7ff:fe57:5af0  prefixlen 64 //cut
        inet6 fe80::268a:7ff:fe57:5af0  prefixlen 64  scopeid 0x20<link>
        inet6 2620:10d:c082:9063::5d2  prefixlen 128  scopeid 0x0<global>
        ether 24:8a:07:57:5a:f0  txqueuelen 1000  (Ethernet)
        RX packets 84249  bytes 6371591 (6.0 MiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 8418  bytes 748781 (731.2 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1000  (Local Loopback)
        RX packets 613  bytes 63906 (62.4 KiB)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 613  bytes 63906 (62.4 KiB)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
[root@localhost ~]# cbmem
36 entries total:

// Lines were cut to avoid checkpatch.pl warnings

Total Time: 96,243,882,140,175,829

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: johnny_lin@wiwynn.com
Change-Id: I29868f03037d1887b90dfb19d15aee83c456edce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Jonathan Zhang 2020-01-16 11:20:09 -08:00 committed by Patrick Georgi
parent 8f89549d3c
commit 75985f1d0c
17 changed files with 1874 additions and 0 deletions
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5
configs/config.ocp_tiogapass Normal file
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CONFIG_VENDOR_OCP=y
CONFIG_BOARD_OCP_TIOGAPASS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"

16
src/mainboard/ocp/Kconfig Normal file
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if VENDOR_OCP
choice
prompt "Mainboard model"
source "src/mainboard/ocp/*/Kconfig.name"
endchoice
source "src/mainboard/ocp/*/Kconfig"
config MAINBOARD_VENDOR
string
default "Open Compute Project"
endif # VENDOR_OCP

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src/mainboard/ocp/Kconfig.name Normal file
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config VENDOR_OCP
bool "Open Compute Project"

45
src/mainboard/ocp/tiogapass/Kconfig Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2019 - 2020 Intel Corporation.
## Copyright (C) 2019 - 2020 Facebook Inc
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_OCP_TIOGAPASS
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ADD_FSP_BINARIES
select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_TABLES
select SOC_INTEL_XEON_SP
select MAINBOARD_USES_FSP2_0
select FSP_CAR
config MAINBOARD_DIR
string
default "ocp/tiogapass"
config MAINBOARD_PART_NUMBER
string
default "TiogaPass"
config MAINBOARD_FAMILY
string
default "TiogaPass"
config FMDFILE
string
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
endif # BOARD_OCP_TIOGAPASS

2
src/mainboard/ocp/tiogapass/Kconfig.name Normal file
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config BOARD_OCP_TIOGAPASS
bool "TiogaPass"

22
src/mainboard/ocp/tiogapass/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2019 - 2020 Intel Corporation.
## Copyright (C) 2019 - 2020 Facebook Inc
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ramstage-y += ramstage.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
CPPFLAGS_common += -Isrc/mainboard/$(MAINBOARDDIR)/
CPPFLAGS_common += -I$(CONFIG_FSP_HEADER_PATH)

382
src/mainboard/ocp/tiogapass/acpi/platform.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 - 2020 Intel Corporation.
* Copyright (C) 2019 - 2020 Facebook Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Enable ACPI _SWS methods */
#include <soc/intel/common/acpi/acpi_wake_source.asl>
Name (_S0, Package (0x04) // mandatory system state
{
0x00, 0x00, 0x00, 0x00
})
Name (_S5, Package (0x04) // mandatory system state
{
0x07, 0x00, 0x00, 0x00
})
/* The APM port can be used for generating software SMIs */
OperationRegion (APMP, SystemIO, 0xb2, 2)
Field (APMP, ByteAcc, NoLock, Preserve)
{
APMC, 8, // APM command
APMS, 8 // APM status
}
/* Port 80 POST */
OperationRegion (DBG0, SystemIO, 0x80, 0x02)
Field (DBG0, ByteAcc, Lock, Preserve)
{
IO80, 8,
IO81, 8
}
/* IO-Trap at 0x800.
* This is the ACPI->SMI communication interface.
*/
OperationRegion (IO_T, SystemIO, 0x800, 0x10)
Field (IO_T, ByteAcc, NoLock, Preserve)
{
Offset (0x8),
TRP0, 8 /* IO-Trap at 0x808 */
}
OperationRegion (PSYS, SystemMemory, 0x6D081000, 0x0400)
Field (PSYS, ByteAcc, NoLock, Preserve)
{
PLAT, 32, // Platform ID
// IOAPIC
APC0, 1, // PCH IOAPIC Enable
AP00, 1, // PC00 IOAPIC Enable
AP01, 1, // PC01 IOAPIC Enable
AP02, 1, // PC02 IOAPIC Enable
AP03, 1, // PC03 IOAPIC Enable
AP04, 1, // PC04 IOAPIC Enable
AP05, 1, // PC05 IOAPIC Enable
AP06, 1, // PC06 IOAPIC Enable
AP07, 1, // PC07 IOAPIC Enable
AP08, 1, // PC08 IOAPIC Enable
AP09, 1, // PC09 IOAPIC Enable
AP10, 1, // PC10 IOAPIC Enable
AP11, 1, // PC11 IOAPIC Enable
AP12, 1, // PC12 IOAPIC Enable
AP13, 1, // PC13 IOAPIC Enable
AP14, 1, // PC14 IOAPIC Enable
AP15, 1, // PC15 IOAPIC Enable
AP16, 1, // PC16 IOAPIC Enable
AP17, 1, // PC17 IOAPIC Enable
AP18, 1, // PC18 IOAPIC Enable
AP19, 1, // PC19 IOAPIC Enable
AP20, 1, // PC20 IOAPIC Enable
AP21, 1, // PC21 IOAPIC Enable
AP22, 1, // PC22 IOAPIC Enable
AP23, 1, // PC23 IOAPIC Enable
RESA, 7,
SKOV, 1, // Override Socket APIC Id
RES0, 7,
// Power Management
TPME, 1,
CSEN, 1,
C3EN, 1,
C6EN, 1,
C7EN, 1,
MWOS, 1,
PSEN, 1,
EMCA, 1,
HWAL, 2,
KPRS, 1,
MPRS, 1,
TSEN, 1,
FGTS, 1,
OSCX, 1,
RESX, 1,
// RAS
CPHP, 8,
IIOP, 8,
IIOH, 64,
PRBM, 32,
P0ID, 32,
P1ID, 32,
P2ID, 32,
P3ID, 32,
P4ID, 32,
P5ID, 32,
P6ID, 32,
P7ID, 32,
P0BM, 64,
P1BM, 64,
P2BM, 64,
P3BM, 64,
P4BM, 64,
P5BM, 64,
P6BM, 64,
P7BM, 64,
MEBM, 16,
MEBC, 16,
CFMM, 32,
TSSY, 32, // TODO: This is TSSZ in system booted from production FW
M0BS, 64,
M1BS, 64,
M2BS, 64,
M3BS, 64,
M4BS, 64,
M5BS, 64,
M6BS, 64,
M7BS, 64,
M0RN, 64,
M1RN, 64,
M2RN, 64,
M3RN, 64,
M4RN, 64,
M5RN, 64,
M6RN, 64,
M7RN, 64,
SMI0, 32,
SMI1, 32,
SMI2, 32,
SMI3, 32,
SCI0, 32,
SCI1, 32,
SCI2, 32,
SCI3, 32,
MADD, 64,
CUU0, 128,
CUU1, 128,
CUU2, 128,
CUU3, 128,
CUU4, 128,
CUU5, 128,
CUU6, 128,
CUU7, 128,
CPSP, 8,
ME00, 128,
ME01, 128,
ME10, 128,
ME11, 128,
ME20, 128,
ME21, 128,
ME30, 128,
ME31, 128,
ME40, 128,
ME41, 128,
ME50, 128,
ME51, 128,
ME60, 128,
ME61, 128,
ME70, 128,
ME71, 128,
MESP, 16,
LDIR, 64,
PRID, 32,
AHPE, 8,
// VTD
DHRD, 192,
ATSR, 192,
RHSA, 192,
// SR-IOV
WSIC, 8,
WSIS, 16,
WSIB, 8,
WSID, 8,
WSIF, 8,
WSTS, 8,
WHEA, 8,
// BIOS Guard
BGMA, 64,
BGMS, 8,
BGIO, 16,
BGIL, 8,
CNBS, 8,
// USB3
XHMD, 8,
SBV1, 8,
SBV2, 8,
// HWPM
HWEN, 2,
ACEN, 1,
HWPI, 1,
RES1, 4,
// IIO
BB00, 8,
BB01, 8,
BB02, 8,
BB03, 8,
BB04, 8,
BB05, 8,
BB06, 8,
BB07, 8,
BB08, 8,
BB09, 8,
BB10, 8,
BB11, 8,
BB12, 8,
BB13, 8,
BB14, 8,
BB15, 8,
BB16, 8,
BB17, 8,
BB18, 8,
BB19, 8,
BB20, 8,
BB21, 8,
BB22, 8,
BB23, 8,
BB24, 8,
BB25, 8,
BB26, 8,
BB27, 8,
BB28, 8,
BB29, 8,
BB30, 8,
BB31, 8,
BB32, 8,
BB33, 8,
BB34, 8,
BB35, 8,
BB36, 8,
BB37, 8,
BB38, 8,
BB39, 8,
BB40, 8,
BB41, 8,
BB42, 8,
BB43, 8,
BB44, 8,
BB45, 8,
BB46, 8,
BB47, 8,
SGEN, 8,
SG00, 8,
SG01, 8,
SG02, 8,
SG03, 8,
SG04, 8,
SG05, 8,
SG06, 8,
SG07, 8,
// Performance
CLOD, 8,
// XTU
XTUB, 32,
XTUS, 32,
XMBA, 32,
DDRF, 8,
RT3S, 8,
RTP0, 8,
RTP3, 8,
// FPGA
FBB0, 8,
FBB1, 8,
FBB2, 8,
FBB3, 8,
FBB4, 8,
FBB5, 8,
FBB6, 8,
FBB7, 8,
FBL0, 8,
FBL1, 8,
FBL2, 8,
FBL3, 8,
FBL4, 8,
FBL5, 8,
FBL6, 8,
FBL7, 8,
P0FB, 8,
P1FB, 8,
P2FB, 8,
P3FB, 8,
P4FB, 8,
P5FB, 8,
P6FB, 8,
P7FB, 8,
FMB0, 32,
FMB1, 32,
FMB2, 32,
FMB3, 32,
FMB4, 32,
FMB5, 32,
FMB6, 32,
FMB7, 32,
FML0, 32,
FML1, 32,
FML2, 32,
FML3, 32,
FML4, 32,
FML5, 32,
FML6, 32,
FML7, 32,
FKPB, 32,
FKB0, 8,
FKB1, 8,
FKB2, 8,
FKB3, 8,
FKB4, 8,
FKB5, 8,
FKB6, 8,
FKB7, 8
}
/* SMI I/O Trap */
Method (TRAP, 1, Serialized)
{
Store (Arg0, SMIF) // SMI Function
Store (0, TRP0) // Generate trap
Return (SMIF) // Return value of SMI handler
}
/*
* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
*
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
Method (_PIC, 1)
{
/* Remember the OS' IRQ routing choice. */
Store (Arg0, PICM)
}
/*
* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method (_PTS, 1)
{
}
/* The _WAK method is called on system wakeup */
Method (_WAK, 1)
{
Return (Package (){ 0, 0 })
}

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src/mainboard/ocp/tiogapass/acpi_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2014 - 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <intelblocks/acpi.h>
#include <soc/acpi.h>
extern const unsigned char AmlCode[];
void acpi_create_gnvs(global_nvs_t *gnvs)
{
acpi_init_gnvs(gnvs);
}

11
src/mainboard/ocp/tiogapass/board.fmd Normal file
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FLASH 32M {
SI_ALL@0x0 0xa36000 {
SI_DESC@0x0 0x1000
SI_ME@0x1000 0xa23000
PLATFORM_DATA@0xa26000 0x10000
}
SI_BIOS@0x1000000 0x1000000 {
FMAP@0x0 0x800
COREBOOT(CBFS)@0x800 0xfff800
}
}

5
src/mainboard/ocp/tiogapass/board_info.txt Normal file
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Board name: TiogaPass
Category: server
ROM protocol: SPI
ROM socketed: yes
Release year: 2018

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src/mainboard/ocp/tiogapass/devicetree.cb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2019 - 2020 Intel Corporation.
## Copyright (C) 2019 - 2020 Facebook Inc
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip soc/intel/xeon_sp
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
register "pirqc_routing" = "PCH_IRQ11"
register "pirqd_routing" = "PCH_IRQ11"
register "pirqe_routing" = "PCH_IRQ11"
register "pirqf_routing" = "PCH_IRQ11"
register "pirqg_routing" = "PCH_IRQ11"
register "pirqh_routing" = "PCH_IRQ11"
# configure device interrupt routing
register "ir00_routing" = "0x3210" # IR00, Dev31
register "ir01_routing" = "0x3210" # IR01, Dev30
register "ir02_routing" = "0x3210" # IR02, Dev29
register "ir03_routing" = "0x3210" # IR03, Dev28
register "ir04_routing" = "0x3210" # IR04, Dev27
# configure interrupt polarity control
register "ipc0" = "0x00ff4000" # IPC0, PIRQA-H (IRQ16-23) should always be ActiveLow
register "ipc1" = "0x00000000" # IPC1
register "ipc2" = "0x00000000" # IPC2
register "ipc3" = "0x00000000" # IPC3
# configure MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT_CORES msrs
# FB production turbo_ratio_limit is 0x1f1f1f2022222325
register "turbo_ratio_limit" = "0x1b1b1b1d20222325"
# FB production turbo_ratio_limit_cores is 0x1c1812100c080402
register "turbo_ratio_limit_cores" = "0x1c1814100c080402"
# configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL
register "pstate_req_ratio" = "0xa"
# configure VTD
register "vtd_support" = "1"
register "coherency_support" = "1"
register "ats_support" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # Host bridge
device pci 04.0 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.1 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.2 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.3 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.4 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.5 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.6 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 04.7 on end # Intel Corporation SkyLake-E CBDMA Registers
device pci 05.0 on end # Intel Corporation SkyLake-E MM/Vt-d Configuration Registers
device pci 05.2 on end # Intel Corporation Device 2025
device pci 05.4 on end # Intel Corporation Device 2026
device pci 08.0 on end # Intel Corporation SkyLake-E Ubox Registers
device pci 08.1 on end # Intel Corporation SkyLake-E Ubox Registers
device pci 08.2 on end # Intel Corporation SkyLake-E Ubox Registers
device pci 11.0 on end # Intel Corporation C620 Series Chipset Family MROM 0
device pci 11.1 on end # Intel Corporation C620 Series Chipset Family MROM 1
device pci 11.5 on end # Intel Corporation C620 Series Chipset Family SSATA Controller [AHCI mode]
device pci 14.0 on end # Intel Corporation C620 Series Chipset Family USB 3.0 xHCI Controller
device pci 16.0 on end # Intel Corporation C620 Series Chipset Family MEI Controller #1
device pci 16.1 on end # Intel Corporation C620 Series Chipset Family MEI Controller #2
device pci 16.4 on end # Intel Corporation C620 Series Chipset Family MEI Controller #3
device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode]
device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1
device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5
device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller
end
end

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src/mainboard/ocp/tiogapass/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 - 2020 Intel Corporation.
* Copyright (C) 2019 - 2020 Facebook Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, // DSDT revision: ACPI v2.0 and up
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 // OEM revision
)
{
// platform ACPI tables
#include "acpi/platform.asl"
// global NVS and variables
#include <soc/intel/xeon_sp/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
// Xeon-SP ACPI tables
Scope (\_SB) {
#include <soc/intel/xeon_sp/acpi/uncore.asl>
}
}

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src/mainboard/ocp/tiogapass/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 - 2020 Intel Corporation.
* Copyright (C) 2019 - 2020 Facebook Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <soc/acpi.h>
void motherboard_fill_fadt(acpi_fadt_t *fadt)
{
fadt->reserved = 0;
fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER;
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 - 2020 Intel Corporation.
* Copyright (C) 2019 - 2020 Facebook Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/ramstage.h>
void mainboard_silicon_init_params(FSPS_UPD *params)
{
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 - 2020 Intel Corporation.
* Copyright (C) 2019 - 2020 Facebook Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <fsp/api.h>
#include <FspmUpd.h>
#include <soc/romstage.h>
#include "skxsp_tp_gpio.h"
#include "skxsp_tp_iio.h"
/*
* Configure GPIO depend on platform
*/
static void mainboard_config_gpios(FSPM_UPD *mupd)
{
mupd->FspmConfig.GpioConfig.GpioTable = (UPD_GPIO_INIT_CONFIG *) tp_gpio_table;
mupd->FspmConfig.GpioConfig.NumberOfEntries =
sizeof(tp_gpio_table)/sizeof(UPD_GPIO_INIT_CONFIG);
}
static void mainboard_config_iio(FSPM_UPD *mupd)
{
mupd->FspmConfig.IioBifurcationConfig.IIoBifurcationTable =
(UPD_IIO_BIFURCATION_DATA_ENTRY *) tp_iio_bifur_table;
mupd->FspmConfig.IioBifurcationConfig.NumberOfEntries =
ARRAY_SIZE(tp_iio_bifur_table);
mupd->FspmConfig.IioPciConfig.ConfigurationTable =
(UPD_PCI_PORT_CONFIG *) tp_iio_pci_port_skt0;
mupd->FspmConfig.IioPciConfig.NumberOfEntries =
ARRAY_SIZE(tp_iio_pci_port_skt0);
mupd->FspmConfig.PchPciConfig.PciPortConfig =
(UPD_PCH_PCIE_PORT *) tp_pch_pci_port_skt0;
mupd->FspmConfig.PchPciConfig.NumberOfEntries =
ARRAY_SIZE(tp_pch_pci_port_skt0);
mupd->FspmConfig.PchPciConfig.RootPortFunctionSwapping = 0x00;
mupd->FspmConfig.PchPciConfig.PciePllSsc = 0x00;
}
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
mainboard_config_gpios(mupd);
mainboard_config_iio(mupd);
}

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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 - 2020 Intel Corporation.
* Copyright (C) 2019 - 2020 Facebook Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SKXSP_TP_IIO_H_
#define _SKXSP_TP_IIO_H_
#include <FspmUpd.h>
#include <soc/pci_devs.h>
/*
* Standard Tioga Pass Iio Bifurcation Table
* This is SS 2x16 config. As documented in OCP TP spec, there are
* 3 configs. SS 2x16 is the most common.
* TODO: figure out config through board SKU ID and through PCIe
* config GPIO setting (SLT_CFG0 / SLT_CFG1).
*/
static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
{ Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, /* 1A x16 */
{ Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, /* 2A x16 */
{ Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, /* 3A x16 */
{ Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
{ Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
{ Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxxxx }, /* no IOU0 */
{ Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxxxx }, /* no IOU1 */
{ Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, /* 3A x8, 3C x8 */
{ Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
{ Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
};
/*
* Standard Tioga Pass Iio PCIe Port Table
*/
static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
// PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload |
// DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd |
// NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 |
// NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 |
// NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride
{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
};
/*
* Standard Tioga Pass PCH PCIe Port Table
*/
static const UPD_PCH_PCIE_PORT tp_pch_pci_port_skt0[] = {
//PortIndex ; ForceEnable ; PortLinkSpeed
{ 0x00, 0x00, PcieAuto },
{ 0x04, 0x00, PcieAuto },
{ 0x05, 0x00, PcieAuto },
};
#endif /* _SKXSP_TP_IIO_H_ */