soc/intel/apollolake: Add handler for SCI

This patch adds the handler to enable bit for gpio_tier1_sci_en.
gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS
bit to generate a wake event and/or an SCI or SMI#. We are setting
the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit
if set from BIOS. As per ACPI spec _GPE is defined as the Named
Object  that evaluates to either an integer or a package. If _GPE
evaluates to an integer, the value is the bit assignment of the SCI
interrupt within the GPEx_STS register of a GPE block described in
the FADT that the embedded controller will trigger. FADT right now
has no mechanism to acheive the same.

Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15578
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2016-07-07 14:48:21 -07:00 committed by Aaron Durbin
parent e51e1045e4
commit 7f149c7bb4
1 changed files with 10 additions and 0 deletions

View File

@ -142,3 +142,13 @@ scope (\_SB) {
}
}
}
Scope(\_GPE)
{
/* Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads
* _L0F in scope GPE it sets bit for gpio_tier1_sci_en in acpi enable
* register at 0x430. For APL acpi enable register DW0 i.e., ACPI
* GPE0a_EN at 0x430 is reserved.
*/
Method(_L0F, 0) {}
}