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util/autoport: Separate NB and SB PCIe port IDs 

The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe
root ports. Put the latter on sandybridge.go instead, and add missing
IDs.

Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2019-02-10 19:52:51 +01:00 committed by Felix Held
parent 11949990a8
commit 8296fdd979
2 changed files with 13 additions and 6 deletions
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11
util/autoport/bd82x6x.go
View File

@ -430,12 +430,11 @@ func init() {
/* PCIe bridge */
for _, id := range []uint16{
0x0151, 0x0155, 0x1c10, 0x1c12,
0x1c14, 0x1c16, 0x1c18, 0x1c1a,
0x1c1c, 0x1c1e, 0x1e10, 0x1e12,
0x1e14, 0x1e16, 0x1e18, 0x1e1a,
0x1e1c, 0x1e1e, 0x1e25, 0x244e,
0x2448,
0x1c10, 0x1c12, 0x1c14, 0x1c16,
0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
0x1e10, 0x1e12, 0x1e14, 0x1e16,
0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
0x1e25, 0x244e, 0x2448,
} {
RegisterPCI(0x8086, id, GenericPCI{})
}

8
util/autoport/sandybridge.go
View File

@ -139,4 +139,12 @@ func init() {
} {
RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}})
}
/* PCIe bridge */
for _, id := range []uint16{
0x0101, 0x0105, 0x0109, 0x010d,
0x0151, 0x0155, 0x0159, 0x015d,
} {
RegisterPCI(0x8086, id, GenericPCI{})
}
}