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soc/intel/xeon_sp: Prepare for CBnT BPM generation 

To generate a working BPM, boot policy manifest for Intel CBnT the
tool that generates it, requires ACPI base and PCH PWRM base as input.
Therefore make it a Kconfig symbol, that can be used in Makefile.inc.

Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2021-03-25 15:59:49 +01:00
parent 6362df3f5e
commit 83a55930dd
2 changed files with 14 additions and 2 deletions
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12
src/soc/intel/xeon_sp/Kconfig
View File

@ -82,6 +82,18 @@ config MAX_CPUS
int
default 80
config INTEL_ACPI_BASE_ADDRESS
hex
default 0x500
help
IO Address of ACPI.
config INTEL_PCH_PWRM_BASE_ADDRESS
hex
default 0xfe000000
help
PCH PWRM Base address.
config PCR_BASE_ADDRESS
hex
default 0xfd000000

4
src/soc/intel/xeon_sp/include/soc/iomap.h
View File

@ -19,7 +19,7 @@
#define SPI_BASE_SIZE 0x1000
#define TCO_BASE_ADDRESS 0x400
#define ACPI_BASE_ADDRESS 0x500
#define ACPI_BASE_ADDRESS CONFIG_INTEL_ACPI_BASE_ADDRESS
#define ACPI_BASE_SIZE 0x100
/* Video RAM */
@ -31,7 +31,7 @@
#define HECI1_BASE_ADDRESS 0xfed1a000
#define PCH_PWRM_BASE_ADDRESS 0xfe000000
#define PCH_PWRM_BASE_ADDRESS CONFIG_INTEL_PCH_PWRM_BASE_ADDRESS
#define PCH_PWRM_BASE_SIZE 0x10000
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS