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mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCES 

This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-03-12 12:52:42 -07:00 committed by Patrick Georgi
parent 7b97289d56
commit 8996b277ab
1 changed files with 1 additions and 15 deletions
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16
src/mainboard/intel/adlrvp/Kconfig
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@ -2,6 +2,7 @@ if BOARD_INTEL_ADLRVP_P || BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_M |
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select ADL_ENABLE_USB4_PCIE_RESOURCES
select BOARD_ROMSIZE_KB_32768 select BOARD_ROMSIZE_KB_32768
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
@ -84,21 +85,6 @@ config ADL_INTEL_EC
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if VBOOT select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if VBOOT
endchoice endchoice
config PCIEXP_HOTPLUG
default y
config PCIEXP_HOTPLUG_BUSES
int
default 42
config PCIEXP_HOTPLUG_MEM
hex
default 0xc200000 # 194 MiB
config PCIEXP_HOTPLUG_PREFETCH_MEM
hex
default 0x1c000000 # 448 MiB
config VBOOT config VBOOT
select VBOOT_LID_SWITCH select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA select VBOOT_MOCK_SECDATA