soc/intel/apollolake: Implement reset_prepare()
At first boot CSE spends long time preparing media for use. As result it may not be able to deal with a CPU reset. Add reset_prepare() callback that polls CSE readiness. BUG=chrome-os-partner:55055 TEST=build with release version of fsp, reboot, observe polling for CSE, then proper reboot happening Change-Id: I639ef900b97132f1a7f269bb864d70009df9fdfe Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -13,11 +13,47 @@
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <reset.h>
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#include <soc/heci.h>
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#include <soc/pm.h>
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#include <timer.h>
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#define CSE_WAIT_MAX_MS 1000
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void global_reset(void)
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{
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global_reset_enable(1);
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hard_reset();
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}
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void reset_prepare(void)
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{
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struct stopwatch sw;
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/*
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* If CSE state is something else than 'normal', it is probably in some
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* recovery state. In this case there is no point in waiting for it to
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* get ready so we cross fingers and reset.
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*/
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if (!heci_cse_normal()) {
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printk(BIOS_DEBUG, "CSE is not in normal state, resetting\n");
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return;
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}
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/* Reset if CSE is ready */
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if (heci_cse_done())
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return;
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printk(BIOS_SPEW, "CSE is not yet ready, waiting\n");
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stopwatch_init_msecs_expire(&sw, CSE_WAIT_MAX_MS);
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while (!heci_cse_done()) {
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if (stopwatch_expired(&sw)) {
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printk(BIOS_SPEW, "CSE timed out. Resetting\n");
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return;
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}
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mdelay(1);
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}
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printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
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}
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