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superio/winbond/w83627uhg: Depreciate romstage component 

Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Convert dependent board to generic winbond serial init. Note the clock
function is actually invalid since it never enters into PNP config mode
to twiddle the register. Further, 48MHz is the default (page 9 of
data-sheet) and so romstage.c need not do anything to the clock rate
hence why it presumably works with this invalid function.

Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5725
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
This commit is contained in:
Edward O'Callaghan 2014-05-13 23:52:30 +10:00 committed by Idwer Vollering
parent b918623f2e
commit 92da206532
4 changed files with 5 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/asrock/imb-a180/romstage.c
View File

@ -35,7 +35,8 @@
#include "southbridge/amd/agesa/hudson/hudson.h" #include "southbridge/amd/agesa/hudson/hudson.h"
#include "cpu/amd/agesa/s3_resume.h" #include "cpu/amd/agesa/s3_resume.h"
#include "cbmem.h" #include "cbmem.h"
#include "superio/winbond/w83627uhg/early_serial.c" #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627uhg/w83627uhg.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
@ -80,9 +81,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x30); post_code(0x30);
post_code(0x31); post_code(0x31);
/* Set w83627uhg to 48MHz and enable w83627uhg */ /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
w83627uhg_set_input_clk_sel(SERIAL_DEV, 0); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
w83627uhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init(); console_init();
} }

1
src/superio/winbond/w83627uhg/Makefile.inc
View File

@ -19,4 +19,3 @@
## ##
ramstage-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.c

57
src/superio/winbond/w83627uhg/early_serial.c
View File

@ -1,57 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Dynon Avionics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include "w83627uhg.h"
static void pnp_enter_ext_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0x87, port);
outb(0x87, port);
}
static void pnp_exit_ext_func_mode(device_t dev)
{
u16 port = dev >> 8;
outb(0xaa, port);
}
/** Set the input clock to 24 or 48 MHz. */
static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz)
{
u8 value;
value = pnp_read_config(dev, 0x24);
value &= ~(1 << 6);
if (!speed_24mhz)
value |= (1 << 6);
pnp_write_config(dev, 0x24, value);
}
static void w83627uhg_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}

2
src/superio/winbond/w83627uhg/w83627uhg.h
View File

@ -37,4 +37,4 @@
#define W83627UHG_SP5 14 /* Com5 */ #define W83627UHG_SP5 14 /* Com5 */
#define W83627UHG_SP6 15 /* Com6 */ #define W83627UHG_SP6 15 /* Com6 */
#endif #endif /* SUPERIO_WINBOND_W83627UHG_W83627UHG_H */