new cache_as_ram support

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/i386/include/arch/romcc_io.h

@@ -178,6 +178,24 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev)
 	return PCI_DEV_INVALID;
 }
 
+static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+{
+        device_t dev, last;
+
+        dev = PCI_DEV(bus, 0, 0);
+        last = PCI_DEV(bus, 31, 7);
+
+        for(; dev <=last; dev += PCI_DEV(0,0,1)) {
+                unsigned int id;
+                id = pci_read_config32(dev, 0);
+                if (id == pci_id) {
+                        return dev;
+                }
+        }
+        return PCI_DEV_INVALID;
+}
+
+
 
 /* Generic functions for pnp devices */
 static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value)

src/config/Options.lb

@@ -280,11 +280,17 @@ define DCACHE_RAM_BASE
 	comment "Base address of data cache when using it for temporary RAM"
 end
 define DCACHE_RAM_SIZE
-	default none
+	default 0x1000
 	format "0x%x"
-	export used
+	export always
 	comment "Size of data cache when using it for temporary RAM"
 end
+define DCACHE_RAM_GLOBAL_VAR_SIZE
+	default 0
+	format "0x%x"
+	export always
+	comment "Size of region that for global variable of cache as ram stage"
+end
 define XIP_ROM_BASE
 	default 0
 	format "0x%x"
@@ -310,7 +316,7 @@ define CONFIG_UNCOMPRESSED
 end
 define CONFIG_LB_MEM_TOPK
 	format "%d"
-	default 1024
+	default 2048
 	export always
 	comment "Kilobytes of memory to initialized before executing code from RAM"
 end

src/cpu/amd/car/cache_as_ram.inc

@@ -1,8 +1,10 @@
 /* by yhlu 6.2005 */
 /* yhlu 2005.12 make it support HDT Memory Debuggers with Disassmbly, please select the PCI Bus mem for Phys Type*/
-/* We may need 4K bytes only */
+/* yhlu 2006.3 copy data from cache to ram and reserve 0x1000 for global variables */
 #define CacheSize DCACHE_RAM_SIZE
 #define CacheBase (0xd0000 - CacheSize)
+/* leave some space for global variable to pass to RAM stage */
+#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
 
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
@@ -147,7 +149,7 @@ clear_fixed_var_mtrr_out:
 #endif /*USE_FALLBACK_IMAGE == 1*/
 
 	/* set up the stack pointer */
-	movl	$(CacheBase+CacheSize-4), %eax
+	movl	$(CacheBase+CacheSize - 4 - GlobalVarSize), %eax 
 	movl    %eax, %esp
 
 	/* Restore the BIST result */

src/cpu/amd/car/clear_init_ram.c

@@ -0,0 +1,59 @@
+/* by yhlu 6.2005 */
+/* be warned, this file will be used core 0/node 0 only */
+
+static void __attribute__((noinline)) clear_init_ram(void)
+{
+	// gcc 3.4.5 will inline the copy_and_run and clear_init_ram in post_cache_as_ram
+	// will reuse %edi as 0 from clear_memory for copy_and_run part, actually it is increased already
+	// so noline clear_init_ram
+        clear_memory(0,  ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE));
+
+}
+
+/* be warned, this file will be used by core other than core 0/node 0 or core0/node0 when cpu_reset*/
+static inline __attribute__((always_inline)) void set_init_ram_access(void)
+{
+        __asm__ volatile (
+
+	"pushl %%ecx\n\t"
+	"pushl %%edx\n\t"
+	"pushl %%eax\n\t"
+
+        /* enable caching for first 1M using variable mtrr */
+        "movl    $0x200, %%ecx\n\t"
+        "xorl    %%edx, %%edx\n\t"
+        "movl     $(0 | 6), %%eax\n\t"
+//      "movl     $(0 | MTRR_TYPE_WRBACK), %%eax\n\t"
+        "wrmsr\n\t"
+
+        "movl    $0x201, %%ecx\n\t"
+        "movl    $0x0000000f, %%edx\n\t"
+#if CONFIG_USE_INIT
+        "movl    %%esi, %%eax\n\t"
+#else
+        "movl    $((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800), %%eax\n\t"
+#endif
+        "wrmsr\n\t"
+
+#if 0
+        /* enable caching for 64K using fixed mtrr */
+        "movl    $0x26e, %%ecx\n\t"  /* fix4k_f0000*/
+        "movl    $0x1e1e1e1e, %%eax\n\t" /* WB MEM type */
+        "movl    %%eax, %%edx\n\t"
+        "wrmsr\n\t"
+        "movl    $0x26f, %%ecx\n\t" /* fix4k_f8000*/
+        "wrmsr\n\t"
+#endif
+
+	"popl	%%eax\n\t"
+	"popl   %%edx\n\t"
+	"popl	%%ecx\n\t"
+
+        :
+        :
+#if CONFIG_USE_INIT
+        "S"((~(( 0 + (CONFIG_LB_MEM_TOPK<<10) ) -1)) | 0x800)
+#endif
+        );
+}
+

src/cpu/amd/car/copy_and_run.c

@@ -37,7 +37,7 @@ static inline void print_debug_cp_run(const char *strval, uint32_t val)
 #endif
 }
 
-static void copy_and_run(unsigned cpu_reset)
+static void copy_and_run(void)
 {
 	uint8_t *src, *dst; 
         unsigned long ilen = 0, olen = 0, last_m_off =  1;
@@ -54,7 +54,7 @@ static void copy_and_run(unsigned cpu_reset)
 		"subl %1, %2\n\t"
 		: "=a" (src), "=b" (dst), "=c" (olen)
 	);
-	memcpy(src, dst, olen);
+	memcpy(dst, src, olen);
 #else 
 
         __asm__ volatile (
@@ -65,14 +65,13 @@ static void copy_and_run(unsigned cpu_reset)
 
 	print_debug_cp_run("src=",(uint32_t)src); 
 	print_debug_cp_run("dst=",(uint32_t)dst);
-	
-//	dump_mem(src, src+0x100);
 
         for(;;) {
                 unsigned int m_off, m_len;
                 while(GETBIT(bb, src, ilen)) {
                         dst[olen++] = src[ilen++];
                 }
+
                 m_off = 1;
                 do {
                         m_off = m_off*2 + GETBIT(bb, src, ilen);
@@ -109,24 +108,13 @@ static void copy_and_run(unsigned cpu_reset)
                 }
         }
 #endif
-//	dump_mem(dst, dst+0x100);
 
 	print_debug_cp_run("linxbios_ram.bin length = ", olen);
 
 	print_debug("Jumping to LinuxBIOS.\r\n");
 
-	if(cpu_reset == 1 ) {
+        __asm__ volatile (
-		__asm__ volatile (
+                "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
-			"movl $0xffffffff, %ebp\n\t"
-		);
-	}
-	else {
-                __asm__ volatile (
-                        "xorl %ebp, %ebp\n\t"
-                );
-	}
-	
-	__asm__ volatile (
 		"cli\n\t"
 		"leal    _iseg, %edi\n\t"
 		"jmp     *%edi\n\t"

src/cpu/amd/car/disable_cache_as_ram.c

@@ -3,10 +3,7 @@
 static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
 {
         __asm__ volatile (
-	/* 
+
-	FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
-		It is only needed if we want to go back
-	*/
         /* We don't need cache as ram for now on */
         /* disable cache */
         "movl    %cr0, %eax\n\t"
@@ -43,5 +40,30 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
         "movl    %cr0, %eax\n\t"
         "andl    $0x9fffffff,%eax\n\t"
         "movl    %eax, %cr0\n\t"
+
         );
 }
+/* be warned, this file will be used core 0 / node 0 and ram stack is ready*/
+
+static void disable_cache_as_ram_bsp(void)
+{
+        __asm__ volatile (
+
+        "pushl	%ecx\n\t"
+        "pushl 	%edx\n\t"
+        "pushl 	%eax\n\t"
+
+	);
+
+	disable_cache_as_ram();
+
+	__asm__ volatile (
+
+        "popl   %eax\n\t"
+        "popl   %edx\n\t"
+        "popl   %ecx\n\t"
+
+        );
+}
+
+

src/cpu/amd/car/post_cache_as_ram.c

@@ -1,7 +1,9 @@
-
+/* 2005.6 by yhlu 
+ * 2006.3 yhlu add copy data from CAR to ram
+ */
 #include "cpu/amd/car/disable_cache_as_ram.c"
 
-#include "cpu/amd/car/clear_1m_ram.c"
+#include "cpu/amd/car/clear_init_ram.c"
 
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
@@ -12,11 +14,18 @@ static inline void print_debug_pcar(const char *strval, uint32_t val)
 #endif
 }
 
-
+static void inline __attribute__((always_inline))  memcopy(void *dest, const void *src, unsigned long bytes)
-
-static void post_cache_as_ram(unsigned cpu_reset)
 {
+        __asm__ volatile(
+                "cld\n\t"
+                "rep movsl\n\t"
+                : /* No outputs */
+                : "S" (src), "D" (dest), "c" ((bytes)>>2)
+                );
+}
 
+static void post_cache_as_ram(void)
+{
 
 #if 1
         {
@@ -30,60 +39,50 @@ static void post_cache_as_ram(unsigned cpu_reset)
         }
 #endif
 
-        print_debug_pcar("cpu_reset = ",cpu_reset);
+	unsigned testx = 0x5a5a5a5a;
+	print_debug_pcar("testx = ", testx);
 
-        if(cpu_reset == 0) {
+	/* copy data from cache as ram to 
-                print_debug("Clearing initial memory region: ");
+		ram need to set CONFIG_LB_MEM_TOPK to 2048 and use var mtrr instead.
-        }
+	 */
-        print_debug("No cache as ram now - ");
+#if CONFIG_LB_MEM_TOPK <= 1024
+        #error "You need to set CONFIG_LB_MEM_TOPK greater than 1024"
+#endif
+	
+	set_init_ram_access();
 
-        /* store cpu_reset to ebx */
+	print_debug("Copying data from cache to ram -- switching to use ram as stack... ");
+
+	/* from here don't store more data in CAR */
         __asm__ volatile (
-                "movl %0, %%ebx\n\t"
+        	"pushl  %eax\n\t"
-                ::"a" (cpu_reset)
         );
-
+        memcopy((CONFIG_LB_MEM_TOPK<<10)-DCACHE_RAM_SIZE, DCACHE_RAM_BASE, DCACHE_RAM_SIZE); //inline
-	disable_cache_as_ram();
-
-        if(cpu_reset==0) { // cpu_reset don't need to clear it 
-		clear_1m_ram();
-        }
-	else {
-		set_1m_ram();
-	}
-
         __asm__ volatile (
                 /* set new esp */ /* before _RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- (CONFIG_LB_MEM_TOPK<<10) )
+        ); // We need to push %eax to the stack (CAR) before copy stack and pop it later after copy stack and change esp
+        __asm__ volatile (
+	        "popl   %eax\n\t"
         );
+	/* We can put data to stack again */
 
-        {
+        /* only global variable sysinfo in cache need to be offset */
-                unsigned new_cpu_reset;
+        print_debug("Done\r\n");
+        print_debug_pcar("testx = ", testx);
 
-                /* get back cpu_reset from ebx */
+	print_debug("Disabling cache as ram now \r\n");
-                __asm__ volatile (
+	disable_cache_as_ram_bsp();  
-                        "movl %%ebx, %0\n\t"
-                        :"=a" (new_cpu_reset)
-                );
 
-                print_debug("Use Ram as Stack now - "); /* but We can not go back any more, we lost old stack data in cache as ram*/
+        print_debug("Clearing initial memory region: ");
+        clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10)), that is used as stack in ram
+        print_debug("Done\r\n");
 
-                if(new_cpu_reset==0) {
+        /*copy and execute linuxbios_ram */
-                        print_debug("done\r\n");
+        copy_and_run();
-                } else
+        /* We will not return */
-                {
-                        print_debug("\r\n");
-                }
-
-                print_debug_pcar("new_cpu_reset = ", new_cpu_reset);
-
-
-                /*copy and execute linuxbios_ram */
-                copy_and_run(new_cpu_reset);
-                /* We will not return */
-        }
 
 	print_debug("should not be here -\r\n");
 

src/cpu/amd/model_fxx/init_cpus.c

@@ -1,7 +1,6 @@
 //it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
 #ifndef K8_SET_FIDVID
 	#define K8_SET_FIDVID 0
-	
 #endif
 
 #ifndef K8_SET_FIDVID_CORE0_ONLY
@@ -42,7 +41,7 @@ static void for_each_ap(unsigned bsp_apicid, unsigned core0_only, process_ap_t p
                 j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3);
                 if(nb_cfg_54) {
  	               if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation 
-        	               e0_later_single_core = is_e0_later_in_bsp(i);  // single core
+       	               e0_later_single_core = is_e0_later_in_bsp(i);  // single core
                        } 
                        if(e0_later_single_core) {
                                 j=1;
@@ -204,7 +203,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 		/* get the apicid, it may be lifted already */
 		apicid = lapicid();
 
-#if 1 
+#if 0 
 		// show our apicid, nodeid, and coreid
 		if( id.coreid==0 ) {
 			if (id.nodeid!=0) //all core0 except bsp
@@ -219,21 +218,9 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 #endif
 
                 if (cpu_init_detectedx) {
-		#if RAMINIT_SYSINFO == 1
+                        print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from ");
-			//We need to init sblnk and sbbusn, because it is called before ht_setup_chains_x
+                        print_debug("\r\nIssuing SOFT_RESET...\r\n");
-		        sysinfo->sblnk = get_sblnk();
+                        soft_reset();
-			sysinfo->sbbusn = node_link_to_bus(0, sysinfo->sblnk);
-		#endif
-			print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detect from ");
-
-			print_debug("\r\nIssuing SOFT_RESET...\r\n");
-
-			#if RAMINIT_SYSINFO == 1
-                        soft_reset(sysinfo);
-			#else
-			soft_reset();
-			#endif
-
                 }
 
 		if(id.coreid==0) {
@@ -256,8 +243,8 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
 			wait_cpu_state(bsp_apicid, 0x44);
 			lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu
 
+			set_init_ram_access(); //inline
 			disable_cache_as_ram(); // inline
-			set_1m_ram(); // inline
                         stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... 
                 }
 

src/cpu/x86/lapic/lapic_cpu_init.c

@@ -25,7 +25,7 @@
  */ 
 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
 {
-	return (unsigned long)orig_start_eip & 0xfffff; // 20 bit 
+	return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 
 }
 
 static void copy_secondary_start_to_1m_below(void) 
@@ -43,7 +43,7 @@ static void copy_secondary_start_to_1m_below(void)
         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
 
         /* copy the _secondary_start to the ram below 1M*/
-        memcpy(start_eip, (unsigned long)_secondary_start, code_size);
+        memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
 
         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
 #endif
@@ -117,7 +117,12 @@ static int lapic_start_cpu(unsigned long apicid)
 		return 0;
 	}
 
+#if _RAMBASE >= 0x100000
 	start_eip = get_valid_start_eip((unsigned long)_secondary_start);
+#else
+	start_eip = (unsigned long)_secondary_start;
+#endif
+
 	printk_debug("start_eip=0x%08lx\n", start_eip);
        
 	num_starts = 2;

src/devices/hypertransport.c

@@ -424,17 +424,8 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
 		}
 
 		flags &= ~0x1f; /* mask out base Unit ID */
-#if CK804_DEVN_BASE==0  
-               if((dev->vendor == 0x10de) && (dev->device == 0x005e)) {
-                       next_unitid = 0;
-               } 
-               else {
-#endif
                        flags |= next_unitid & 0x1f;
                        pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
-#if CK804_DEVN_BASE==0 
-               }
-#endif
 
 		/* Update the Unitd id in the device structure */
 		static_count = 1;
@@ -473,11 +464,6 @@ unsigned int hypertransport_scan_chain(struct bus *bus,
 			dev->vendor, dev->device, 
 			(dev->enabled? "enabled": "disabled"), next_unitid);
 
-#if CK804_DEVN_BASE==0 
-		if ((dev->vendor == 0x10de) && (dev->device == 0x005e)) {
-                      break; // CK804 can not change unitid, so it only can be alone in the link
-                }
-#endif
 
 	} while((last_unitid != next_unitid) && (next_unitid <= (max_devfn >> 3)));
  end_of_chain:

src/include/cpu/x86/mem.h

@@ -4,15 +4,13 @@
 /* Optimized generic x86 assembly for clearing memory */
 static inline void clear_memory(void *addr, unsigned long size)
 {
-	asm volatile(
+        asm volatile(
-		"1: \n\t"
+                "cld \n\t"
-		"movl %0, (%1)\n\t"
+                "rep stosl\n\t"
-		"addl $4, %1\n\t"
+                : /* No outputs */
-		"subl $4, %2\n\t"
+                : "a" (0), "D" (addr), "c" (size>>2)
-		"jnz 1b\n\t"
+                );
-		: /* No outputs */
+
-		: "a" (0), "D" (addr), "c" (size)
-		);
 }
 
 #endif /* CPU_X86_MEM_H */

src/mainboard/agami/aruma/cache_as_ram_auto.c

@@ -204,7 +204,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 	unsigned bsp_apicid = 0;
 	struct mem_controller ctrl[8];
 	unsigned nodes;
@@ -253,6 +252,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 
 }

src/mainboard/amd/serengeti_leopard/Config.lb

@@ -117,8 +117,6 @@ if HAVE_ACPI_TABLES
         end
 end
 
-object reset.o
-
 if USE_DCACHE_RAM
 
 	if CONFIG_USE_INIT

src/mainboard/amd/serengeti_leopard/cache_as_ram_auto.c

@@ -10,21 +10,13 @@
 //use by raminit
 #define K8_4RANK_DIMM_SUPPORT 1
 
-//use bu init_cpus
-#if 0
-        #define ENABLE_APIC_EXT_ID 1
-        #define APIC_ID_OFFSET 0x10
-        #define LIFT_BSP_APIC_ID 0
-#else
-        #define ENABLE_APIC_EXT_ID 0
-#endif
-
 //used by incoherent_ht
 //#define K8_SCAN_PCI_BUS 1
 //#define K8_ALLOCATE_IO_RANGE 1
 
 #include <stdint.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
@@ -33,7 +25,6 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
 
 #if 0
 static void post_code(uint8_t value) {
@@ -47,7 +38,6 @@ static void post_code(uint8_t value) {
 #endif
 
 #include <cpu/amd/model_fxx_rev.h> 
-#include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
@@ -66,43 +56,11 @@ static void post_code(uint8_t value) {
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-{
-        device_t dev;
-	unsigned sblnk = get_sblnk();
-
-        /* Find the device */
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 3);
-#else
-	dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 3);
-#endif
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-static void soft_reset(void)
-{
-        device_t dev;
-	unsigned sblnk = get_sblnk();
-
-        /* Find the device */
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-        dev = PCI_DEV(node_link_to_bus(0, sblnk), 2 + HT_CHAIN_END_UNITID_BASE - 1, 0);
-#else
-        dev = PCI_DEV(node_link_to_bus(0, sblnk), 4 + HT_CHAIN_UNITID_BASE - 1, 0);
-#endif
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -254,7 +212,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 	unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -296,7 +253,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        	if (needs_reset) {
                	print_info("ht reset -\r\n");
-               	soft_reset();
+		soft_reset();
        	}
 
 	allow_all_aps_stop(bsp_apicid);
@@ -327,6 +284,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_pci_devices();
 #endif
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 
 }

src/mainboard/arima/hdama/Config.lb

@@ -45,7 +45,6 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 ##
 ## Romcc output

src/mainboard/broadcom/blast/cache_as_ram_auto.c

@@ -190,7 +190,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 	unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -269,6 +268,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	dump_pci_devices();
 #endif
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 
 }

src/mainboard/tyan/s2850/Config.lb

@@ -44,7 +44,6 @@ driver mainboard.o
 
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 if USE_DCACHE_RAM
 

src/mainboard/tyan/s2850/cache_as_ram_auto.c

@@ -47,31 +47,7 @@ static void post_code(uint8_t value) {
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -200,7 +176,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 
         if (bist == 0) {
 		init_cpus(cpu_init_detectedx);
@@ -235,5 +210,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }

src/mainboard/tyan/s2875/Config.lb

@@ -44,7 +44,6 @@ driver mainboard.o
 
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 if USE_DCACHE_RAM
 

src/mainboard/tyan/s2875/cache_as_ram_auto.c

@@ -36,32 +36,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-static void hard_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -198,7 +173,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 
         if (bist == 0) {
 		init_cpus(cpu_init_detectedx);
@@ -231,6 +205,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 
 }

src/mainboard/tyan/s2880/Config.lb

@@ -44,7 +44,6 @@ driver mainboard.o
 
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 if USE_DCACHE_RAM
 

src/mainboard/tyan/s2880/cache_as_ram_auto.c

@@ -37,31 +37,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -197,7 +173,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 
         if (bist == 0) {
 		init_cpus(cpu_init_detectedx);
@@ -232,5 +207,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }

src/mainboard/tyan/s2881/Config.lb

@@ -44,7 +44,6 @@ driver mainboard.o
 object get_bus_conf.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 if USE_DCACHE_RAM
 
 if CONFIG_USE_INIT

src/mainboard/tyan/s2881/cache_as_ram_auto.c

@@ -42,31 +42,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -185,7 +161,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
         unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -234,5 +209,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
         sdram_initialize(nodes, ctrl);
 
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }

src/mainboard/tyan/s2882/Config.lb

@@ -44,7 +44,6 @@ driver mainboard.o
 
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 if USE_DCACHE_RAM
 

src/mainboard/tyan/s2882/cache_as_ram_auto.c

@@ -36,31 +36,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -200,7 +176,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 
         if (bist == 0) {
 		init_cpus(cpu_init_detectedx);
@@ -235,6 +210,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 
 }

src/mainboard/tyan/s2885/Config.lb

@@ -44,7 +44,6 @@ driver mainboard.o
 object get_bus_conf.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 
 if USE_DCACHE_RAM
 

src/mainboard/tyan/s2885/cache_as_ram_auto.c

@@ -36,31 +36,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -185,7 +161,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
         unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -234,6 +209,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
         memreset_setup();
         sdram_initialize(nodes, ctrl);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 
 }

src/mainboard/tyan/s2891/Config.lb

@@ -237,7 +237,7 @@ chip northbridge/amd/amdk8/root_complex
                                         	                io 0x60 = 0x2f8
                                                 	        irq 0x70 = 3
 	                                                end
-        	                                        device pnp 2e.5 off #  Keyboard
+        	                                        device pnp 2e.5 on #  Keyboard
                 	                                        io 0x60 = 0x60
                         	                                io 0x62 = 0x64
                                 	                        irq 0x70 = 1
@@ -314,7 +314,7 @@ chip northbridge/amd/amdk8/root_complex
 					#	chip drivers/ati/ragexl
                                                 chip drivers/pci/onboard
                                                         device pci 7.0 on end
-                                        #                register "rom_address" = "0xfff80000" #for 512K
+                                               #         register "rom_address" = "0xfff80000" #for 512K
 							register "rom_address" = "0xfff00000" #for 1M
                                                 end
 					end

src/mainboard/tyan/s2891/Options.lb

@@ -54,6 +54,7 @@ uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HT_FREQ_1G_SUPPORT
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
@@ -66,6 +67,13 @@ uses LIFT_BSP_APIC_ID
 
 uses CONFIG_PCI_64BIT_PREF_MEM
 
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses CONFIG_LB_MEM_TOPK
+
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
 #default ROM_SIZE=524288
@@ -131,6 +139,22 @@ default CONFIG_LOGICAL_CPUS=1
 #1G memory hole
 default K8_HW_MEM_HOLE_SIZEK=0x100000
 
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0
+
+#make the SB HT chain on bus 0, default is not (0)
+default K8_SB_HT_CHAIN_ON_BUS0=2
+
+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+
 #BTEXT Console
 #default CONFIG_CONSOLE_BTEXT=1
 
@@ -144,9 +168,9 @@ default CONFIG_PCI_ROM_RUN=1
 default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=1
+default CONFIG_USE_INIT=0
 
-default ENABLE_APIC_EXT_ID=1
+default ENABLE_APIC_EXT_ID=0
 default APIC_ID_OFFSET=0x10
 default LIFT_BSP_APIC_ID=0
 

src/mainboard/tyan/s2891/cache_as_ram_auto.c

@@ -42,25 +42,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
-{
-        set_bios_reset();
-
-        /* full reset */
-	outb(0x0a, 0x0cf9);
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        set_bios_reset();
-#if 1
-        /* link reset */
-	outb(0x02, 0x0cf9);
-        outb(0x06, 0x0cf9);
-#endif
-}
-
 static void memreset_setup(void)
 {
 }
@@ -197,7 +178,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
         unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -246,5 +226,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }

src/mainboard/tyan/s2891/get_bus_conf.c

@@ -152,9 +152,10 @@ void get_bus_conf(void)
                 else {
                         printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
 
-                        bus_8131_0 = bus_ck804_5+1;
                 }
 
+		bus_8131_0 = (pci1234[1] >> 16) & 0xff;
+
                 /* 8131-1 */
                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
                 if (dev) {

src/mainboard/tyan/s2891/resourcemap.c

@@ -186,7 +186,7 @@ static void setup_s2891_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+//		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000,
 		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, 
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -216,7 +216,7 @@ static void setup_s2891_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n 
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
+//		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
 		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,

src/mainboard/tyan/s2892/Config.lb

@@ -313,7 +313,8 @@ chip northbridge/amd/amdk8/root_complex
 					#	chip drivers/ati/ragexl
 						chip drivers/pci/onboard
 							device pci 6.0 on end
-							register "rom_address" = "0xfff80000"
+                                                #       register "rom_address" = "0xfff80000" #for 512K
+                                                        register "rom_address" = "0xfff00000" #for 1M
 						end
                                                 chip drivers/pci/onboard
                                                         device pci 8.0 on end

src/mainboard/tyan/s2892/Options.lb

@@ -54,18 +54,24 @@ uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
 uses K8_HW_MEM_HOLE_SIZEK
+uses K8_HT_FREQ_1G_SUPPORT
 
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses CONFIG_USE_INIT
 
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
-default ROM_SIZE=524288
+#default ROM_SIZE=524288
 
 #1M bytes
-#default ROM_SIZE=1048576
+default ROM_SIZE=1048576
 
 
 ##
@@ -125,6 +131,21 @@ default CONFIG_LOGICAL_CPUS=1
 #1G memory hole
 default K8_HW_MEM_HOLE_SIZEK=0x100000
 
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0
+
+#make the SB HT chain on bus 0, default is not (0)
+default K8_SB_HT_CHAIN_ON_BUS0=2
+
+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
 #BTEXT Console
 #default CONFIG_CONSOLE_BTEXT=1
 
@@ -138,8 +159,7 @@ default CONFIG_PCI_ROM_RUN=1
 default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=1
+default CONFIG_USE_INIT=0
-
 
 ##
 ## Build code to setup a generic IOAPIC

src/mainboard/tyan/s2892/cache_as_ram_auto.c

@@ -36,25 +36,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
-{
-        set_bios_reset();
-
-        /* full reset */
-	outb(0x0a, 0x0cf9);
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        set_bios_reset();
-#if 1
-        /* link reset */
-	outb(0x02, 0x0cf9);
-        outb(0x06, 0x0cf9);
-#endif
-}
-
 static void memreset_setup(void)
 {
 }
@@ -210,7 +191,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 
         if (bist == 0) {
 		init_cpus(cpu_init_detectedx);
@@ -246,5 +226,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }

src/mainboard/tyan/s2892/get_bus_conf.c

@@ -152,9 +152,9 @@ void get_bus_conf(void)
                 else {
                         printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
 
-                        bus_8131_0 = bus_ck804_5+1;
                 }
 
+		bus_8131_0 = (pci1234[1] >> 16) & 0xff;
                 /* 8131-1 */
                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
                 if (dev) {

src/mainboard/tyan/s2895/Options.lb

@@ -64,12 +64,17 @@ uses ENABLE_APIC_EXT_ID
 uses APIC_ID_OFFSET
 uses LIFT_BSP_APIC_ID
 
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
-default ROM_SIZE=524288
+#default ROM_SIZE=524288
 
 #1M bytes
-#default ROM_SIZE=1048576
+default ROM_SIZE=1048576
 
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
@@ -134,6 +139,18 @@ default K8_HW_MEM_HOLE_SIZEK=0x100000
 #Opteron K8 1G HT Support
 default K8_HT_FREQ_1G_SUPPORT=1
 
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0
+
+#make the SB HT chain on bus 0, default is not (0)
+default K8_SB_HT_CHAIN_ON_BUS0=2
+
+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
 #VGA
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
@@ -144,7 +161,7 @@ default CONFIG_PCI_ROM_RUN=1
 default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=1
+default CONFIG_USE_INIT=0
 
 default ENABLE_APIC_EXT_ID=1
 default APIC_ID_OFFSET=0x10

src/mainboard/tyan/s2895/cache_as_ram_auto.c

@@ -50,25 +50,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
 
-static void hard_reset(void)
-{
-        set_bios_reset();
-
-        /* full reset */
-	outb(0x0a, 0x0cf9);
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        set_bios_reset();
-#if 1
-        /* link reset */
-	outb(0x02, 0x0cf9);
-        outb(0x06, 0x0cf9);
-#endif
-}
-
 static void memreset_setup(void)
 {
 }
@@ -239,7 +220,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
         unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -288,5 +268,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }

src/mainboard/tyan/s4880/Config.lb

@@ -43,7 +43,6 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 if USE_DCACHE_RAM
 
 	if CONFIG_USE_INIT

src/mainboard/tyan/s4880/cache_as_ram_auto.c

@@ -36,31 +36,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 2), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -247,7 +223,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
 
         if (bist == 0) {
 		init_cpus(cpu_init_detectedx);
@@ -281,5 +256,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }

src/mainboard/tyan/s4882/Config.lb

@@ -43,7 +43,6 @@ arch i386 end
 driver mainboard.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-object reset.o
 if USE_DCACHE_RAM
 
 	if CONFIG_USE_INIT

src/mainboard/tyan/s4882/cache_as_ram_auto.c

@@ -36,31 +36,8 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void hard_reset(void)
-{
-        device_t dev;
 
-        /* Find the device */
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-        dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
-
-        set_bios_reset();
-
-        /* enable cf9 */
-        pci_write_config8(dev, 0x41, 0xf1);
-        /* reset */
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        device_t dev;
-
-        /* Find the device */
-        dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
-
-        set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
-}
 
 static void memreset_setup(void)
 {
@@ -222,7 +199,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
         unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -271,6 +247,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 
 }

src/northbridge/amd/amdk8/coherent_ht.c

@@ -1,3 +1,10 @@
+#if USE_DCACHE_RAM
+
+#include "coherent_ht_car.c"
+
+#else
+
+
 /* coherent hypertransport initialization for AMD64 
  * 
  * written by Stefan Reinauer <stepan@openbios.org>
@@ -1824,3 +1831,5 @@ static int setup_coherent_ht_domain(void)
 	result.needs_reset = optimize_link_read_pointers(result.nodes, result.needs_reset);
 	return result.needs_reset;
 }
+
+#endif

src/northbridge/amd/amdk8/incoherent_ht.c

@@ -968,34 +968,4 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
 #endif
 
 
-static unsigned get_sblnk(void)
-{
-        uint32_t reg;
-        /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
-        reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
-        return ((reg>>8) & 3) ;
-}
-
-/* Look up a which bus a given node/link combination is on.
- * return 0 when we can't find the answer.
- */
-
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        unsigned reg;
-
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                unsigned config_map;
-                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-                if ((config_map & 3) != 3) {
-                        continue;
-                }
-                if ((((config_map >> 4) & 7) == node) &&
-                        (((config_map >> 8) & 3) == link))
-                {
-                        return (config_map >> 16) & 0xff;
-                }
-        }
-        return 0;
-}
 

src/northbridge/amd/amdk8/raminit.c

@@ -18,6 +18,10 @@
 #define K8_4RANK_DIMM_SUPPORT 0
 #endif
 
+#if USE_DCACHE_RAM == 1
+static void hard_reset(void);
+#endif
+
 #if 1
 static void setup_resource_map(const unsigned int *register_values, int max)
 {

src/northbridge/amd/amdk8/reset_test.c

@@ -51,3 +51,37 @@ static void set_bios_reset(void)
 	htic &= ~HTIC_BIOSR_Detect;
 	pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
 }
+
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+        unsigned reg;
+
+        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+                unsigned config_map;
+                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+                if ((config_map & 3) != 3) {
+                        continue;
+                }
+                if ((((config_map >> 4) & 7) == node) &&
+                        (((config_map >> 8) & 3) == link))
+                {
+                        return (config_map >> 16) & 0xff;
+                }
+        }
+        return 0;
+}
+
+static unsigned get_sblk(void)
+{
+        uint32_t reg;
+        /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
+        reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
+        return ((reg>>8) & 3) ;
+}
+
+static unsigned get_sbbusn(unsigned sblk)
+{
+	return node_link_to_bus(0, sblk);
+}
+
+

src/southbridge/amd/amd8111/Config.lb

@@ -9,3 +9,4 @@ driver amd8111_ac97.o
 driver amd8111_nic.o
 driver amd8111_pci.o
 driver amd8111_smbus.o
+object amd8111_reset.o

src/southbridge/amd/amd8111/amd8111_early_ctrl.c

@@ -1,10 +1,31 @@
 /* by yhlu 2005.10 */
-static void hard_reset(struct sys_info *sysinfo)
+static unsigned get_sbdn(unsigned bus)
 {
         device_t dev;
-	
+
-        /* Find the device */
+        /* Find the device.
-        dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 3);
+         * There can only be one 8111 on a hypertransport chain/bus.
+         */
+        dev = pci_locate_device_on_bus(
+                PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+                bus);
+
+        return (dev>>15) & 0x1f;
+
+}
+
+static void hard_reset(void)
+{
+        device_t dev;
+        unsigned bus;
+
+        /* Find the device.
+         * There can only be one 8111 on a hypertransport chain/bus.
+         */
+        bus = get_sbbusn(get_sblk());
+        dev = pci_locate_device_on_bus(
+                PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ACPI),
+                bus);
 
         set_bios_reset();
 
@@ -14,11 +35,11 @@ static void hard_reset(struct sys_info *sysinfo)
         outb(0x0e, 0x0cf9);
 }
 
-static void enable_fid_change_on_sb(struct sys_info *sysinfo)
+static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
         device_t dev;
-        /* Find the device */
+
-        dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 3);
+	dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
 
         pci_write_config8(dev, 0x74, 4);
 
@@ -27,15 +48,25 @@ static void enable_fid_change_on_sb(struct sys_info *sysinfo)
 
 }
 
-static void soft_reset(struct sys_info *sysinfo)
+static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 {
         device_t dev;
-        
-	/* Find the device */
-        dev = PCI_DEV(sysinfo->sbbusn, sysinfo->sbdn+1, 0);
 
+	dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
+
+        /* Reset */
         set_bios_reset();
         pci_write_config8(dev, 0x47, 1);
+
 }
 
+static void soft_reset(void)
+{
 
+	unsigned sblk = get_sblk();
+	unsigned sbbusn = get_sbbusn(sblk);
+	unsigned sbdn = get_sbdn(sbbusn);
+
+	return soft_reset_x(sbbusn, sbdn);
+
+}

src/southbridge/amd/amd8111/amd8111_lpc.c

@@ -70,10 +70,12 @@ static void setup_ioapic(void)
 	unsigned long ioapic_base = 0xfec00000;
 	volatile unsigned long *l;
 	struct ioapicreg *a = ioapicregvalues;
+	unsigned long bsp_apicid = lapicid();
 
 	l = (unsigned long *) ioapic_base;
 
-	ioapicregvalues[0].value_high = lapicid()<<(56-32); 
+	ioapicregvalues[0].value_high = bsp_apicid<<(56-32);
+	printk_debug("amd8111: ioapic bsp_apicid = %02x\n", bsp_apicid); 
 	
 	for (i = 0; i < sizeof(ioapicregvalues) / sizeof(ioapicregvalues[0]);
 	     i++, a++) {
@@ -88,7 +90,7 @@ static void setup_ioapic(void)
 			return;
 		}
 		printk_spew("for IRQ, reg 0x%08x value 0x%08x 0x%08x\n", 
-			a->reg, a->value_low, a->value_high);
+			    a->reg, a->value_low, a->value_high);
 	}
 }
 
@@ -179,7 +181,7 @@ static void amd8111_lpc_enable_resources(device_t dev)
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	pci_write_config32(dev, 0x70, 
-		((device & 0xffff) << 16) | (vendor & 0xffff));
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {

src/southbridge/amd/amd8111/amd8111_reset.c

@@ -1,5 +1,3 @@
-/* Include this file in the mainboards reset.c
- */
 #include <arch/io.h>
 #include <device/pci_ids.h>
 
@@ -38,7 +36,7 @@ static unsigned pci_read_config32(device_t dev, unsigned where)
 }
 
 #define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_locate_device(unsigned pci_id, unsigned bus)
+static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
 {
 	device_t dev, last;
 	dev = PCI_DEV(bus, 0, 0);
@@ -55,35 +53,19 @@ static device_t pci_locate_device(unsigned pci_id, unsigned bus)
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
 
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-	unsigned reg;
 
-	for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+void hard_reset(void)
-		unsigned config_map;
-		config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
-		if ((config_map & 3) != 3) {
-			continue;
-		}
-		if ((((config_map >> 4) & 7) == node) &&
-			(((config_map >> 8) & 3) == link)) 
-		{
-			return (config_map >> 16) & 0xff;
-		}
-	}
-	return 0;
-}
-
-static void amd8111_hard_reset(unsigned node, unsigned link)
 {
 	device_t dev;
 	unsigned bus;
+        unsigned node = 0;
+        unsigned link = get_sblk();
 
 	/* Find the device.
 	 * There can only be one 8111 on a hypertransport chain/bus.
 	 */
 	bus = node_link_to_bus(node, link);
-	dev = pci_locate_device(
+	dev = pci_locate_device_on_bus(
 		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA), 
 		bus);
 

src/southbridge/nvidia/ck804/ck804_early_setup.c

@@ -383,3 +383,23 @@ static int ck804_early_setup_x(void)
 	ck804_early_clear_port();
 	return set_ht_link_ck804(4);
 }
+
+static void hard_reset(void)
+{
+        set_bios_reset();
+
+        /* full reset */
+        outb(0x0a, 0x0cf9);
+        outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+        set_bios_reset();
+#if 1
+        /* link reset */
+        outb(0x02, 0x0cf9);
+        outb(0x06, 0x0cf9);
+#endif
+}
+

src/southbridge/nvidia/ck804/ck804_early_setup_car.c

@@ -426,3 +426,23 @@ static int ck804_early_setup_x(void)
 	ck804_early_clear_port(ck804_num, busn, io_base);
 	return set_ht_link_ck804(4);
 }
+
+static void hard_reset(void)
+{
+        set_bios_reset();
+
+        /* full reset */
+        outb(0x0a, 0x0cf9);
+        outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+        set_bios_reset();
+#if 1
+        /* link reset */
+        outb(0x02, 0x0cf9);
+        outb(0x06, 0x0cf9);
+#endif
+}
+

src/southbridge/nvidia/ck804/ck804_enable_rom.c

@@ -3,6 +3,7 @@
  *  by yhlu@tyan.com
  */
 
+
 static void ck804_enable_rom(void)
 {
 	unsigned char byte;

src/southbridge/nvidia/ck804/ck804_smbus.h

@@ -29,14 +29,13 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 		unsigned char val;
 		smbus_delay();
 		val = inb(smbus_io_base + SMBHSTSTAT);
-		if ((val & 0x1f) == 0) {
+		val &= 0x1f;
-			break;
+		if (val == 0) {
-		}
+			return 0;
-		if(loops == (SMBUS_TIMEOUT / 2)) {
-			outb((val & 0x1f),smbus_io_base + SMBHSTSTAT);
 		}
+		outb(val,smbus_io_base + SMBHSTSTAT);
 	} while(--loops);
-	return loops?0:-2;
+	return -2;
 }
 
 static int smbus_wait_until_done(unsigned smbus_io_base)
@@ -49,10 +48,10 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 		
 		val = inb(smbus_io_base + SMBHSTSTAT);
 		if ( (val & 0xff) != 0) {
-			break;
+			return 0;
 		}
 	} while(--loops);
-	return loops?0:-3;
+	return -3;
 }
 static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
@@ -200,3 +199,4 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned
         }
         return 0;
 }
+

targets/tyan/s2892/Config.lb

@@ -7,8 +7,10 @@ mainboard tyan/s2892
 
 # Tyan s2892
 romimage "normal"
+#       48K for ATI ROM in 1M
+        option ROM_SIZE = 999424
 #       48K for SCSI FW or ATI ROM
-        option ROM_SIZE = 475136
+#        option ROM_SIZE = 475136
 #       48K for SCSI FW and 48K for ATI ROM
 #       option ROM_SIZE = 425984 
 #       64K for Etherboot

targets/tyan/s2895/Config.lb

@@ -29,8 +29,7 @@ romimage "normal"
 #       payload ../../../payloads/filo.zelf
 #	payload ../../../payloads/tg3.zelf
 #	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
-	payload /tmp/filo.elf
 #	payload ../../../payloads/forcedeth_vga.zelf
 #	payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf
 #	payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf
@@ -59,8 +58,7 @@ romimage "fallback"
 #       payload ../../../payloads/filo.zelf
 #	payload ../../../payloads/tg3.zelf
 #	payload ../../../payloads/tg3--filo_hda2_vga.zelf
-#	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
+	payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
-	payload /tmp/filo.elf
 #	payload ../../../payloads/forcedeth_vga.zelf
 #	payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
 #	payload ../../../payloads/tg3_vga.zelf