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soc/intel/alderlake/acpi: Changing USB ports indexing. 

xhci.asl places the SS ports at 11-14, following HS ports 1-10. However,
for Nissa, the kernel detects 12 HS ports 1-12 and 4 SS ports at 13-16,
resulting in the PLD intended for SS ports 1 and 2 being associated with
HS ports 11 and 12.

Changing the asl for SS to 13-16 makes locations associate correctly and
peering work.

BUG=b:234544025
BRANCH=firmware-brya-14505.B
TEST=manually verified on Nissa and Brya devices

Change-Id: I57aef771a7ff086b71a9e90b81e1a3635f832b2f
Signed-off-by: Adam Mills <adamjmills@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66590
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Adam Mills 2022-08-10 15:49:00 +10:00 committed by Tim Wawrzynczak
parent f43e0e7247
commit 9c4514ba14
1 changed files with 4 additions and 4 deletions
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8
src/soc/intel/alderlake/acpi/xhci.asl
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@ -74,10 +74,10 @@ Device (XHCI)
Device (HS09) { Name (_ADR, 9) }
Device (HS10) { Name (_ADR, 10) }
/* USB3 */
Device (SS01) { Name (_ADR, 11) }
Device (SS02) { Name (_ADR, 12) }
Device (SS03) { Name (_ADR, 13) }
Device (SS04) { Name (_ADR, 14) }
Device (SS01) { Name (_ADR, 13) }
Device (SS02) { Name (_ADR, 14) }
Device (SS03) { Name (_ADR, 15) }
Device (SS04) { Name (_ADR, 16) }
}
#endif
}