mb/google/guybrush: select DISABLE_KEYBOARD_RESET_PIN

Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select
it and remove the temporary workaround that was implemented in the
mainboard code in commit 39ef890336.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Felix Held 2021-03-25 01:26:04 +01:00
parent 27b295b98b
commit a228279ed7
2 changed files with 1 additions and 12 deletions

View File

@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select AMD_SOC_CONSOLE_UART select AMD_SOC_CONSOLE_UART
select BOARD_ROMSIZE_KB_16384 select BOARD_ROMSIZE_KB_16384
select DISABLE_KEYBOARD_RESET_PIN
select DISABLE_SPI_FLASH_ROM_SHARING select DISABLE_SPI_FLASH_ROM_SHARING
select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID select DRIVERS_I2C_HID

View File

@ -1,11 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h> #include <amdblocks/amd_pci_util.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <device/device.h> #include <device/device.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/southbridge.h>
#include <variant/ec.h> #include <variant/ec.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
@ -90,16 +88,6 @@ static void mainboard_configure_gpios(void)
{ {
size_t base_num_gpios, override_num_gpios; size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios;
u32 reg;
/*
* Disable KBRST feature
* KBRSTEN is set to 1 on reset and this causes system reset
* if GPIO 129 is configured as GPO_LOW.
* */
reg = pm_read8(PM_RST_CTRL1);
reg &= ~KBRSTEN;
pm_write8(PM_RST_CTRL1, reg);
base_gpios = variant_base_gpio_table(&base_num_gpios); base_gpios = variant_base_gpio_table(&base_num_gpios);
override_gpios = variant_override_gpio_table(&override_num_gpios); override_gpios = variant_override_gpio_table(&override_num_gpios);