soc/intel/elkhartlake: Provide a way to enable real-time tuning

Intel provides a Real-Time Tuning Guide for Elkhart Lake to improve
real-time behaviour of the SoC (see Intel doc #640979). It describes,
amongst knobs for the OS, a couple of firmware settings that need to be
set properly to reduce latencies in all the subsystems. Things like
clock and power gating as well as low power states for peripherals and
buses are disabled in this scenario.

This patch takes the mentioned UEFI parameters from the guide and
translates them to FSP-M and FSP-S parameters. In addition, a chip
config switch guards this tuning which can be selected on mainboard
level if needed.

When this real-time tuning is enabled, the overall system performance
in a real-time environment can be increased by 2-3%.

Change-Id: Ib524ddd675fb3ea270bacf8cd06cb628e895b4b6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/elkhartlake/chip.h

@@ -465,6 +465,9 @@ struct soc_intel_elkhartlake_config {
 
 	/* Disable L1 prefetcher */
 	bool L1_prefetcher_disable;
+
+	/* Activate real time tuning according to the Real-Time Tuning Guide (doc #640979) */
+	bool realtime_tuning_enable;
 };
 
 typedef struct soc_intel_elkhartlake_config config_t;

src/soc/intel/elkhartlake/fsp_params.c

@@ -307,10 +307,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 */
 	params->EnableTcoTimer = 1;
 
-	/* PCH Master Gating Control */
-	params->PchPostMasterClockGating = 1;
-	params->PchPostMasterPowerGating = 1;
-
+	/* Set up recommended real time parameters if real time tuning is enabled. */
+	if (config->realtime_tuning_enable) {
+		params->PchPostMasterClockGating = 0;
+		params->PchPostMasterPowerGating = 0;
+		params->PchPwrOptEnable = 0;
+		params->PsfTccEnable = 1;
+		params->PmcLpmS0ixSubStateEnableMask = 0;
+		params->PchDmiAspmCtrl = 0;
+		params->PchLegacyIoLowLatency = 0;
+		params->EnableItbm = 0;
+		params->D3ColdEnable = 0;
+		params->PmcOsIdleEnable = 0;
+	} else {
+		params->PchPostMasterClockGating = 1;
+		params->PchPostMasterPowerGating = 1;
+	}
 	/* HECI */
 	params->Heci3Enabled = config->Heci3Enable;
 
@@ -360,6 +372,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		params->PcieRpLtrMaxSnoopLatency[i] = 0x1003;
 		/* Virtual Channel 1 to Traffic Class mapping */
 		params->PcieRpVc1TcMap[i] = 0x60;
+		if (config->realtime_tuning_enable)
+			params->PcieRpEnableCpm[i] = 0;
 	}
 
 	/* SATA config */

src/soc/intel/elkhartlake/romstage/fsp_params.c

@@ -61,8 +61,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 	m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
 
 	/* PCH Master Gating Control */
-	m_cfg->PchMasterClockGating = 1;
-	m_cfg->PchMasterPowerGating = 1;
+	if (config->realtime_tuning_enable) {
+		m_cfg->PchMasterClockGating = 0;
+		m_cfg->PchMasterPowerGating = 0;
+		m_cfg->DisPgCloseIdleTimeout = 0;
+		m_cfg->PowerDownMode = 0;
+	} else {
+		m_cfg->PchMasterClockGating = 1;
+		m_cfg->PchMasterPowerGating = 1;
+	}
 
 	m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS);