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soc/amd/mendocino: Add VRM limit DPTC registers 

Add VRM DPTC limit registers. These are required when throttling the SOC
for low/no battery mode to prevent the SOC from overwhelming the
charger.

b/245942343 is tracking passing these additional fields to the FSP and
having the FSP configure them.

BRANCH=none
BUG=b:217911928
TEST=Build skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Van Patten 2022-09-06 09:56:52 -06:00 committed by Martin L Roth
parent a90aebbf2a
commit b06873f77c
1 changed files with 4 additions and 0 deletions
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4
src/soc/amd/mendocino/chip.h
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@ -56,6 +56,7 @@ struct soc_amd_mendocino_config {
uint16_t stt_error_coeff;
uint16_t stt_error_rate_coefficient;
/* Default */
uint8_t stapm_boost;
uint32_t stapm_time_constant_s;
uint32_t apu_only_sppt_limit;
@ -64,6 +65,9 @@ struct soc_amd_mendocino_config {
uint32_t slow_ppt_limit_mW;
uint32_t slow_ppt_time_constant_s;
uint32_t thermctl_limit_degreeC;
uint32_t vrm_current_limit_mA;
uint32_t vrm_maximum_current_limit_mA;
uint32_t vrm_soc_current_limit_mA;
uint8_t smartshift_enable;